SPEC CPU2026 increases instruction volume and memory footprint while shifting pressure to instruction-cache bottlenecks; 4-5 workload subsets per group preserve 96.4-99.9% of full-suite behavior and show complementary traits to DCPerf and MLPerf.
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EquivFusion unifies equivalence checking across hardware design levels by lowering PyTorch, C/C++, Chisel, Verilog, and netlists via MLIR into SMT-LIB, BTOR2, and AIGER formats.
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SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison
SPEC CPU2026 increases instruction volume and memory footprint while shifting pressure to instruction-cache bottlenecks; 4-5 workload subsets per group preserve 96.4-99.9% of full-suite behavior and show complementary traits to DCPerf and MLPerf.
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EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
EquivFusion unifies equivalence checking across hardware design levels by lowering PyTorch, C/C++, Chisel, Verilog, and netlists via MLIR into SMT-LIB, BTOR2, and AIGER formats.