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arxiv: 2605.03713 · v2 · submitted 2026-05-05 · 💻 cs.AR · cs.PF

Recognition: 2 theorem links

· Lean Theorem

SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison

RuiHao Li , Andrew Jacob , Neeraja J. Yadwadkar , Lizy K. John
Authors on Pith no claims yet

Pith reviewed 2026-05-08 18:48 UTC · model grok-4.3

classification 💻 cs.AR cs.PF
keywords SPEC CPU2026benchmark characterizationrepresentativeness analysisCPU performance evaluationinstruction cache stressworkload subsetscross-suite comparisonmicroarchitectural metrics
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The pith

SPEC CPU2026 increases instruction volume, memory footprint, and instruction-cache pressure compared to SPEC CPU2017, while compact subsets preserve most of its behavior.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper provides the first detailed characterization of the SPEC CPU2026 benchmark suite across nine diverse processor platforms. It reveals that this new suite demands more instructions and memory than its 2017 predecessor and places greater stress on the instruction cache. The authors demonstrate that selecting just 4-5 representative workloads per category can capture 96.4 to 99.9 percent of the full suite's microarchitectural behavior. This allows for more efficient yet faithful CPU performance evaluations. By comparing it to other suites, they position SPEC CPU2026 as a general-purpose benchmark that bridges toward real-world datacenter workloads.

Core claim

We find that, compared to SPEC CPU2017, SPEC CPU2026 increases instruction volume and memory footprint, and shifts pressure toward emerging bottlenecks, most notably higher instruction-cache stress. Using clustering-based representativeness analysis, we identify that compact subsets of 4-5 workloads per group preserve 96.4-99.9% of full-suite behavior, substantially reducing evaluation costs without sacrificing fidelity. SPEC CPU2026 remains a general-purpose suite with complementary characteristics to MLPerf and DCPerf, yet moves closer to real-world CPU behavior than prior generations.

What carries the argument

Clustering-based representativeness analysis on microarchitectural metrics measured across nine platforms, which identifies minimal workload subsets and supports direct cross-suite comparisons.

Load-bearing premise

The nine chosen platforms adequately represent the diversity of modern CPU microarchitectures and the clustering analysis on microarchitectural metrics accurately identifies subsets that preserve all relevant behaviors without missing critical interactions or outliers.

What would settle it

A new processor platform outside the nine shows substantially different ranking or bottleneck behavior when running the proposed compact subsets versus the full suite, or a previously unmeasured metric like energy per instruction deviates sharply from the reported trends.

Figures

Figures reproduced from arXiv: 2605.03713 by Andrew Jacob, Lizy K. John, Neeraja J. Yadwadkar, RuiHao Li.

Figure 1
Figure 1. Figure 1: Key performance metric comparison between view at source ↗
Figure 2
Figure 2. Figure 2: Dendrogram showing similarity between SPEC CPU26 workloads; shorter linkage distance indicates higher similarity. 3.2 Representative Subsets Using the hierarchical clusters, we derive compact workload subsets that preserve the behavioral diversity of the full suite. We first cut each dendrogram at a fixed linkage distance to form groups of behaviorally similar workloads; view at source ↗
Figure 3
Figure 3. Figure 3: Principal Component (PC) comparison across four benchmark suites. The top 8 PCs capture 84% of total variability. view at source ↗
Figure 4
Figure 4. Figure 4: Dendrogram showing DCPerf and MLPerf have view at source ↗
Figure 5
Figure 5. Figure 5: Comparison of key metrics between SPEC CPU26, SPEC CPU17, MLPerf, and DCPerf. Note that SPEC generally offers broader coverage than those domain-specific benchmark suites (this section focuses on geo-mean comparisons for each suite). 4.2 Detailed Microarchitectural Analysis Beyond similarity analysis, we compare microarchitectural be￾havior across SPEC CPU26, SPEC CPU17, DCPerf, and MLPerf using CPU-C4 view at source ↗
Figure 6
Figure 6. Figure 6: Performance impact of alternative memory allocators with/without THP across view at source ↗
Figure 7
Figure 7. Figure 7: RSS for CPU2026/CPU2017 Rate (per-workload data view at source ↗
Figure 8
Figure 8. Figure 8: IPC and DIMM bandwidth across prefetcher configurations. Higher IPC comes from better DIMM bandwidth utilization. view at source ↗
Figure 9
Figure 9. Figure 9: Performance distributions across different compilers for view at source ↗
Figure 10
Figure 10. Figure 10: SPEC CPU17 vs. CPU26 inst count across compilers; CPU26 is more compiler-sensitive (especially 706.stockfish_r). and 1.09× on SPEC CPU26. For FP Rate, gcc-15 slightly regresses on SPEC CPU17 (0.97×) but still improves SPEC CPU26 (1.07×). Exam￾ining IPC and instruction count reveals a key difference between the two suites. On SPEC CPU26, the gains are driven primarily by reduced dynamic instruction count: … view at source ↗
Figure 11
Figure 11. Figure 11: Per-copy retired-instruction distributions across nine machines ( view at source ↗
Figure 12
Figure 12. Figure 12: Scaling distributions (1–40 threads) for view at source ↗
Figure 13
Figure 13. Figure 13: Using the RRR mode to run 709.cactus_r and 749.fo view at source ↗
Figure 14
Figure 14. Figure 14: Detailed per-workload performance of different allocators on view at source ↗
Figure 15
Figure 15. Figure 15: Detailed per-workload performance of different allocators on view at source ↗
Figure 16
Figure 16. Figure 16: Detailed per-workload performance of different compilers on view at source ↗
Figure 17
Figure 17. Figure 17: Detailed per-workload performance of different compilers on view at source ↗
Figure 18
Figure 18. Figure 18: Detailed per-workload performance of Speed workload scaling on view at source ↗
Figure 19
Figure 19. Figure 19: Detailed per-workload performance of Speed workload scaling on view at source ↗
read the original abstract

Specialized accelerators dominate AI workloads, but CPUs remain critical for orchestrating these accelerators and running datacenter services. As a result, CPU performance increasingly shapes end-to-end system efficiency, making it necessary for benchmarks to reflect modern workloads and bottlenecks. However, it remains unclear how emerging CPU benchmark suites reflect these shifts. To address this, we present the first comprehensive characterization of SPEC CPU2026 across nine platforms spanning recent Intel, AMD, Ampere, and Nvidia processors. We find that, compared to SPEC CPU2017, SPEC CPU2026 increases instruction volume and memory footprint, and shifts pressure toward emerging bottlenecks, most notably higher instruction-cache stress. We next examine whether the full suite is necessary for architectural evaluation. Using clustering-based representativeness analysis, we identify that compact subsets of 4-5 workloads per group preserve 96.4-99.9% of full-suite behavior, substantially reducing evaluation costs without sacrificing fidelity. To better position SPEC CPU2026, we compare it against SPEC CPU2017, DCPerf, and MLPerf using cross-suite microarchitectural metrics. SPEC CPU2026 remains a general-purpose suite with complementary characteristics: it is less vector-intensive than MLPerf and has lower frontend pressure than DCPerf, yet moves closer to real-world CPU behavior than prior SPEC CPU generations. Finally, we show that SPEC CPU2026 supports practical architectural studies beyond aggregate scores through case studies on page sizes and allocators, prefetching, compiler optimizations, ISA sensitivity, and many-core scaling. The new round-robin stagger mode generates proxy workloads that approximate DCPerf, reducing the IPC gap to 13.7%. Overall, SPEC CPU2026 sets a new foundation for rigorous and cost-effective CPU evaluation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript provides the first comprehensive characterization of SPEC CPU2026 across nine platforms spanning recent Intel, AMD, Ampere, and Nvidia processors. Compared to SPEC CPU2017, it reports increased instruction volume and memory footprint with a shift toward higher instruction-cache stress. Clustering analysis identifies compact subsets of 4-5 workloads per group that preserve 96.4-99.9% of full-suite behavior. Cross-suite comparisons with SPEC CPU2017, DCPerf, and MLPerf position SPEC CPU2026 as a general-purpose suite with complementary characteristics (less vector-intensive than MLPerf, lower frontend pressure than DCPerf). Case studies demonstrate utility for studies on page sizes, allocators, prefetching, compiler optimizations, ISA sensitivity, and many-core scaling, including a round-robin stagger mode that approximates DCPerf with a 13.7% IPC gap reduction.

Significance. If the empirical results hold, this work is significant for the computer architecture community by updating benchmark understanding for modern CPU workloads that orchestrate accelerators and run datacenter services. The multi-platform measurements provide directional evidence on workload shifts, and the clustering-derived subsets could substantially lower evaluation costs while maintaining high fidelity. The cross-suite positioning and practical case studies offer actionable guidance for benchmark selection and architectural studies. Strengths include direct execution measurements on standard benchmarks across diverse vendors and the introduction of a new stagger mode for proxy workloads.

major comments (2)
  1. [§3 and Abstract] Platform selection (§3 and Abstract): The characterization relies on nine platforms (Intel, AMD, Ampere, Nvidia) to support claims of increased instruction volume, memory footprint, and higher i-cache stress versus CPU2017. However, this selection may under-sample axes such as vector width variations or novel cache coherence protocols, which is load-bearing for the generalizability of the 'shifts pressure toward emerging bottlenecks' claim; the paper should add explicit discussion of platform limitations and sensitivity tests.
  2. [Abstract and §4] Clustering-based representativeness analysis (Abstract and §4): The central cost-effectiveness claim rests on subsets of 4-5 workloads preserving 96.4-99.9% of full-suite behavior via clustering on microarchitectural metrics. The abstract presents these fidelity numbers without error bars, statistical details, full methodology (e.g., chosen metrics, algorithm parameters, or outlier validation), leaving it unclear whether all relevant interactions are captured; this requires expansion to verify the representativeness result.
minor comments (2)
  1. [Abstract] Abstract: Include the exact list of nine platforms and any confidence intervals or methodology summary for the 96.4-99.9% figures to improve clarity and allow immediate assessment of the fidelity claims.
  2. [Cross-suite comparison] Cross-suite comparison section: Specify the precise set of microarchitectural metrics used for positioning against DCPerf and MLPerf to enhance reproducibility.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the positive assessment of the work's significance and for the constructive major comments. We address each point below and will revise the manuscript accordingly to improve clarity and rigor.

read point-by-point responses

  1. Referee: [§3 and Abstract] Platform selection (§3 and Abstract): The characterization relies on nine platforms (Intel, AMD, Ampere, Nvidia) to support claims of increased instruction volume, memory footprint, and higher i-cache stress versus CPU2017. However, this selection may under-sample axes such as vector width variations or novel cache coherence protocols, which is load-bearing for the generalizability of the 'shifts pressure toward emerging bottlenecks' claim; the paper should add explicit discussion of platform limitations and sensitivity tests.

    Authors: We agree that an explicit discussion of platform limitations is warranted to better support the generalizability of our claims regarding workload shifts. In the revised version, we will add a new subsection in §3 that details the rationale for selecting the nine platforms (spanning recent Intel, AMD, Ampere, and Nvidia processors) while acknowledging that they do not exhaustively cover all microarchitectural axes, such as every possible vector width variation or novel cache coherence protocols. We will also incorporate sensitivity tests by reporting how the key trends (increased instruction volume, memory footprint, and i-cache stress) hold consistently across the available platforms, thereby providing directional evidence without overstating universality. revision: yes

  2. Referee: [Abstract and §4] Clustering-based representativeness analysis (Abstract and §4): The central cost-effectiveness claim rests on subsets of 4-5 workloads preserving 96.4-99.9% of full-suite behavior via clustering on microarchitectural metrics. The abstract presents these fidelity numbers without error bars, statistical details, full methodology (e.g., chosen metrics, algorithm parameters, or outlier validation), leaving it unclear whether all relevant interactions are captured; this requires expansion to verify the representativeness result.

    Authors: We will expand §4 with the requested details to make the clustering analysis fully transparent and verifiable. Specifically, we will include: the complete list of microarchitectural metrics used for clustering, the exact algorithm and parameters (e.g., number of clusters and distance metric), outlier validation steps, and statistical measures such as error bars or variance on the reported 96.4-99.9% fidelity values. The abstract will be lightly revised to note that full methodological details and statistical support appear in §4. This expansion will clarify how the 4-5 workload subsets capture relevant interactions while preserving high fidelity to the full suite. revision: yes

Circularity Check

0 steps flagged

Empirical characterization with no circular derivations or self-referential reductions

full rationale

The paper's core claims rest on direct empirical measurements: running SPEC CPU2026 workloads on nine external platforms (Intel, AMD, Ampere, Nvidia) to quantify instruction volume, memory footprint, and i-cache stress relative to SPEC CPU2017, followed by standard clustering on microarchitectural counters to identify compact subsets whose measured behavior is then validated against the full suite (yielding the 96.4-99.9% preservation figures). Cross-suite positioning against DCPerf and MLPerf uses the same external metrics without any fitted parameters renamed as predictions, self-citations invoked for uniqueness theorems, or ansatzes smuggled from prior author work. No derivation step reduces by construction to its own inputs; the representativeness analysis is falsifiable via the reported metric comparisons and remains independent of the paper's conclusions.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The work relies on empirical execution of existing SPEC workloads and standard clustering; one data-driven choice of subset size (4-5) is presented as preserving high fidelity. No new entities postulated.

free parameters (1)
  • subset size per group
    Selected as 4-5 workloads to achieve 96.4-99.9% preservation; appears chosen based on clustering results rather than a priori.
axioms (1)
  • domain assumption SPEC CPU workloads and the chosen microarchitectural metrics adequately capture real-world CPU bottlenecks in datacenter and AI-orchestration scenarios
    Invoked to justify relevance of the suite and the clustering analysis.

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