Deconstruction floor caps FP64 emulation at half the peak on Rubin
Paper identifies the bottleneck as a ratio of three design integers and shows a narrow hardware fix would reach the full 473-TFLOPS roof.
cs.PF
Performance
Covers performance measurement and evaluation, queueing, and simulation. Roughly includes material in ACM Subject Classes D.4.8 and K.6.2.
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KAN training scales like standard deep learning under data parallelism
Study finds 74.7% parallel efficiency and general DDP behavior, not a KAN-specific bottleneck
DALI is 1.17× faster than AlbumentationsX in input pipeline throughput
Both beat TorchVision, Kornia, and Pillow on most recipes, but DALI uses 230 MiB more GPU memory on the common set.
· “RGB Input Pipelines: Throughput, GPU Memory, and Transformation Coverage”
One identity settles how IoT sensors should batch reports
Long-run inference value splits exactly into each report's statistical gain times the chance it arrives by the deadline.
· “Assessing Fixed-Batch Reporting for Deadline-constrained Inference in Intermittently Powered IoT”
Node-local NVMe staging removes two shared-fabric penalties in DL training
DYAD's lazy byte-range caching cuts DataLoader stalls from 28% to 2.9% of iterations and reduces all-reduce contention 145×.
· “Sharing a Fabric with Collective Communication: Two Storage Penalties in Deep Learning Training”
One profiling pass speeds up oversubscribed LLMs 3.1x
AutoUVM prefetches only the tensors kernels actually touch, beating object-level UVM prefetchers by up to 4.7x.
· “AutoUVM: Automated Prefetching Framework for LLMs under UVM Oversubscription”
RAGMark is a modular benchmarking framework that measures per-stage latency
RAGMark enables fine-grained, reproducible benchmarking of RAG pipelines across retrievers, vector databases, reranking, compression, and…
· “RAGMark: A Comprehensive Framework for Benchmarking Retrieval-Augmented Generation Systems”
GreenPipe hits 6.3–9.4% power error on Raspberry Pi DNN inference
Multi-resource regression trained on DNN kernels beats CPU-only baselines by 26.9% average MAPE.
· “GreenPipe: Power Modeling for Containerized DNN Inference on Kubernetes Edge Nodes”
An AI agent writes TPU kernels that beat hand-tuned code
On JaxBench it hits 1.58x speedup over XLA, and on eight production kernels it outruns human Pallas kernels, 2.32x to 2.02x.
AI aces chip-mapping Q&A
Only one of sixteen model families can turn mapping insight into trustworthy performance-model code.
· “PerfReasoning: How Well Do LLMs Reason on Hardware Performance?”
First on-board ML detects methane plumes from airplane
Model runs in 2.6 seconds per scene, leaving time to spare during 67-second data collection windows.
· “On-board ML for Trace Gas detection in Imaging Spectroscopy data”
Hierarchical parallel scheme yields 23% better energy efficiency
Para-Pipe generates Pareto-optimal configurations, improving energy efficiency by 23% on edge SoCs
· “Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs”
Gate beats predictor in cache prefetching safety
Matched controls show a classic stride predictor matches a learned one when gated; proxy gains don't become real speed.
· “Confidence-Gated Admission for Hardware Prefetching: When the Gate Matters More Than the Predictor”
RASER is a user-space framework that runs LLM-based agentic workflows on existing HPC…
RASER uses Slurm job arrays with shared-filesystem work stealing to dynamically balance agent workloads, achieving near-39% faster makespan…
· “RASER: Resilient Agent Scheduling and Execution Runtime for HPC Clusters”
Deterministic parallel commit without knowing read-write sets
Lantern's DAG rule lets every node run the batch on its own — up to 4.2x the throughput of the Aria protocol.
· “Lantern: Finding Committable Transactions via Back-Propagation on DAGs”
New matrix solution for triggered packet queues
M^T/G/1 model handles general service times with exponential triggering delays.
· “Analysis of Triggered Packet Streams: A Matrix-Analytic Method for Exponential Triggering Delays”
eBPF tracer points which container caused CPU wait
No kernel patch needed: measures who ran while the victim waited, using a 16-byte self-describing slice.
Cache hit ratio limit derived for multi-turn LLM conversations
Mean-field formula predicts reuse fraction under LRU policy with asymptotic proof
Scale analysis shows 19% SMT throughput loss in SPEC CPU 2026 on Zen 5
First microarchitectural characterization of the new suite reveals SMT contention, L3 interference, and three workload clusters invisible…
· “Performance Characterization of SPEC CPU 2026 on AMD EPYC 9755 Processor”
DART cuts P99 tail delay by up to 23% on every test graph
One policy unites target choice, route, and en-route service to tame the waits that set the 99th percentile.
· “DART: Aiming for Tail-Delay Control in Reconfigurable Networks”
Keeping bits alive, not arithmetic, is computing's real energy cost
Known memory bounds become real joule floors, and attention's square law meets today's bandwidth wall.
· “The Price of Remembering: A Calibrated Energy Law for Computation”
Two failure modes make stream learners unfit for embedded memory budgets
Adaptive ensembles exceed small budgets immediately; incremental trees grow up to 7× over time.
Loss-aware modular compression cuts perplexity 2.5% on average
Gradient-weighted Fisher statistics in module activation space cut perplexity and lift task accuracy ~1%, training-free.
FFT of sparse matrices boosts kernel selection accuracy by 4%
Spectral features complement spatial stats: tolerant accuracy rises from 75.7% to 79.3% on SuiteSparse, with up to 1.245× speedups on…
· “Spectral Analysis for Sparse Matrix Computation: Insights and Potential”
LLM inference energy per token falls as request energy rises
A fixed-plus-step energy model explains why longer outputs and larger batches hide growing total GPU energy while lowering per-token cost.
· “Characterization of Request and Token Energy Costs for LLM Inference Workloads on GPU Platforms”
One media, stored once: FFSlim cuts multi‑modal training I/O by 5–14%
A lightweight format that groups all texts with their shared media object, eliminating duplication and exploiting page‑cache reuse.
· “FFSlim: An Efficient and Lightweight Format for Multi-modal Data Storage and Retrieval”
Most SPEC CPU2026 benchmarks match upstream performance closely
Systematic comparison shows large divergences come from deliberate removal of intrinsics and I/O, not arbitrary changes.
Jetson NVJPEG chip lifts edge vision throughput by 30 percent
Running JPEG decode on dedicated hardware alongside CPU and DLA removes the preprocessing bottleneck for large images.
· “Accelerating Data Preprocessing for Efficient Vision Model Inference on Jetson Edge Device”
Work–depth–memory model reveals RLM training bottlenecks
Systematic taxonomy of intra- and inter-model parallelism for PPO, GRPO, and DPO pipelines
· “Performance Foundations of Parallel & Distributed Reasoning Language Models”
FoldPipe hides remote I/O with prefetch
Lightweight Python layer overlaps molecular shard retrieval with training, yet 20-pair benchmark finds no reliable wall-clock gain.
· “FoldPipe: Bounded Remote Streaming of Native Molecular Shards with Asynchronous Prefetch”
93% of QoI predictions are well-calibrated from compression metadata
TOPIQ decomposes queries into primitives, enabling post-hoc confidence intervals without per-QoI derivation or retraining.
· “TOPIQ: Statistical Error Propagation for Quantity-of-Interest Prediction under Lossy Compression”
Launch-bound and substitutable: why three MoE optimizations fail
Fused kernels, INT4 quantization, and graph compilation underperform because MoE is launch-bound and experts are interchangeable.
O-RAN's CU and DU show opposite processor responses to traffic
Profiling under matched hardware reveals the CU shifts strongly under load while the DU stays dominated by IQ-sample processing, guiding…
· “PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units”
LLM-written CUDA kernels beat PyTorch eager on 14 operators
An agent harness captures operators from live models, explores 50 revisions per kernel, and falls back to eager when slower.
· “Kernel Forge: An Agent Harness for LLM-based Generation and Optimization of CUDA Kernels”
Fluxion speeds long-context inference 1.5x-3.7x via CPU-GPU hybrid sparse attention
Dynamic output-aware budgeting and priority scheduling keep quality within 0.26 of full attention for CPU-resident KV caches
· “An Efficient Hybrid Sparse Attention with CPU-GPU Parallelism for Long-Context Inference”
Algebraic coarsening delivers 3x speedup in GPU contact solves
In-solve vertex aggregation reduces system size without remeshing or loss of contact accuracy.
· “AGIPC: Adaptive In-Solve Algebraic Coarsening for GPU IPC”
Co-designed transformer cuts CPU decode bandwidth 2x per token
A delay-aware schedule drops critical-path weight traffic from 9.00 to 4.50 MB/token; a 30.9B-parameter MoE decodes at 5.94 tok/s.
FP16 can kick a language model off Apple's Neural Engine
Measured on M1 and M3: a 25.85M conv model streams 0 ANE bytes in fp16 and about 83 percent residency in int8 or 2-bit.
Hidden banded structure: one dispatch check buys N-fold LU speedup
Detecting banded structure in dense storage and converting before factorization yields up to N-fold speedups with constant worst-case…
· “When Structure is Silent: Opportunities for Algorithmic Dispatch in Linear Algebra”
Auto-tuning portable GPU kernels yields 3×–7× speedups
Portable SVD code beats median configurations on NVIDIA, AMD, Intel, and Apple GPUs without vendor rewrites.
· “Portable to Efficient: Auto-Tuning Hardware-Agnostic GPU Kernels in Julia”
One triangular solve replaces per-node state snapshots
For gated-delta hybrids, verifying a draft tree no longer needs a state snapshot per node, and freed HBM buys throughput where memory binds.
· “TreeWY: Speculative Verification for Gated DeltaNet Hybrids”
4-bit model beats its own 16-bit source on 7 of 9 benchmarks
4-bit students trained on the original teacher's logits match or beat their 16-bit sources at a quarter of the memory.
· “Quantization-Aware Healing: A Practical Recipe for Recovering Compressed, 4-Bit LLMs”
Network bandwidth rules Earth-observation storage up to 10 Gbps
Same servers at 1, 10 and 100 Gbps show throughput tracks link rate below 10 Gbps, then memory topology takes over.
Verified inliner: 2.5x optimal
Rocq proof certifies inlining reaches a fixed point in bounded steps, at most 2.5 times the optimal cost.
· “Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics”
A simplex integral speeds queueing-network inference
Exact integral form plus Laplace expansion cut normalizing-constant error below 1% on thousand-job models.
· “Accelerating Performance Inference over Closed Systems by Asymptotic Methods”
30% context retention cuts edge RAG GPU energy by up to 53%
Measurements show generation dominates edge-RAG cost and mild compression loses energy, so rates should be set at runtime.
· “From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG”
Workload, not garbage collector, drives Java energy
Three collectors differed by up to 15% in mean energy, yet ANOVA found no reliable collector effect.
· “Garbage Collection and Energy Consumption in Java: A Controlled Study Across Workloads and JDKs”
Pruned tree computes exact HBM reliability in 1,152 bytes
It matches dynamic programming's expansions while storing at most 17 traversal entries at central demand.
Packing heads into wide vectors gives CPU attention up to 42x speedup
FlashAttention-V breaks the head-dimension barrier on vector CPUs, with 8-11x decode gains and a 64-lane/4096-bit sweet spot.
Shared multi-agent search doubles kernel speedup at same budget
On a paged-attention task, two agents sharing conclusions reach a 290.8x speedup versus 142.6x for one agent.
· “KernelArc: A Multi-Agent Framework for GPU Kernel Optimization”
Ascon-Hash256 is the fastest hash for quantum-safe TOTP logins
TLS 1.3 with ML-KEM and ML-DSA plus HMAC-TOTP: eight hashes benchmarked on PC and Raspberry Pi.
· “Quantum-Safe Web Service Architecture Using Time-Based One-Time Passwords”
LLM rewrites with verification hit 83% accuracy and 16% speedup
A syntax, bounded-model-check, and LLM review chain lets an AI optimizer keep only the loop rewrites it can justify.
· “T-LLM Compiler: Trusted LLM-based Code Optimization and Verification Framework”
Padding restores deterministic LLM output at 15-324% higher throughput
CoRun isolates prefill and pads decode, so the same prompt yields the same tokens no matter what runs alongside it.
· “CoRun: Padding is Simple and Efficient for Deterministic LLM Inference”
LAAB ties every benchmark report to the exact library build
Reports record the build, toolchain, flags, and run settings, so numbers can be trusted and rerun.
· “Performance Reporting of Mathematical Library Installations with LAAB - An Overview”
Unifying data-reduction tricks could cut pipeline costs 1000x
Sketching, sampling, rollups, and compression are one family; treating them together unlocks compounding savings.
· “ASAP: Reimagining the Data Lifecycle using Application Semantic-Aware Processing”
Volunteer devices beat centralized AI serving as user pools grow
Distributed scheduling over user devices improves completion and P99 latency while cutting dedicated server use.
· “User-Assisted Collaborative Distributed Inference for Efficient QoS-Aware Autoscaling”
Cache size alone sets the winning block: 30-59% faster
A block size from L2 capacity and data-type width beats the inherited one, predicted before measuring.
Joint speedups beat the product of isolated gains on 70% of kernels
Perfect-branch and perfect-cache speedups understate headroom when loads and branches couple in the same hot loop.
· “The Fallacy of Independent Ceilings: Characterizing Coupled Load-Branch Stall Interaction”
Serving batch shifts cost-optimal vocabulary 16x
Datacenter LLMs should use 8-16x larger token vocabularies than today, with under 2% quality cost.
One model predicts CNN energy
CARB scores thousands of GPU deployment candidates in seconds and cuts the profiling shortlist by over 90%.
Parse, not copy, throttles GPU LZ77 decode
On an H100, parsing eats 64–72% of decode time; depth caps barely help. The last serial step can be encoded away.
A machine's memory shape can fix matrix-tile sizes
If occupancy fractions become derivable, kernel tuning reduces to reading a data sheet.
GAMP cache policy needs the least memory for target hit rates
It sizes caches by the smallest capacity that meets a service-level hit-rate target, not by a fixed share of data.
Learned eviction keeps 94.2% of accuracy with 25% of cache
A per-step KL-divergence reward trains a tiny policy to retain the tokens that matter, beating fixed heuristics.
· “DistillCache: KL-Guided Adaptive KV-Cache Eviction for Memory-Efficient LLM Inference”
Cutting WebGPU dispatches 36% lifts LLM throughput 53%
A controlled fusion test keeps the same shaders, drops dispatches from 876 to 564, and gains 53% in tokens per second.
· “Measuring and Reducing WebGPU Dispatch Overhead for LLM Inference”
Two fixes halve the accuracy gap of compressed LLMs
Refreshing calibration activations and reranking layers lifts zero-shot scores by up to 2.5 points.
Irregular GPU kernels put Triton 11–31x behind CUDA C++
On a hash-blocked reconstruction kernel, Rust nears CUDA parity; both costs come from language limits.
· “What Irregularity Costs: CUDA C++, Rust, and Triton on a Hash-Blocked GPU Workload”
Quaternion nets beat shallow quantum circuits on vision tasks
Classical SU(2) models match real baselines while depth-3 VQCs lag by up to 9 points on CIFAR-10.
· “Classical SU(2) Models Match or Exceed Shallow Variational Quantum Circuits on Vision Benchmarks”
SmartNIC-side sampling cuts GNN training time up to 62x
Offloading neighbor sampling and FP16 quantization to memory-side SmartNICs shrinks network data; proof-of-concept confirms it.
· “LGNNIC: Acceleration of Large-Scale GNN Training using SmartNICs”
Plots beat text: 2.5x less energy
Visual time-series inputs cut inference cost 1.8-2.5x while lifting F1 on telecom and public benchmarks.
First peer-benchmarked index scores AI token efficiency
TEI turns cache and model-tier usage into a 0–100 score with actionable savings estimates.
· “The Token Efficiency Index: A Peer-Benchmarked Composite Indicator for AI Token Efficiency”
Three counters predict how any workload reacts to new memory
Fit once per machine; one baseline run then gives CPI on HBM, CXL, or any memory latency
· “Aneto: Predicting System Performance by Exploiting Cross-Workload Regularity”
Routing to cleanest grid halves modeled LLM inference emissions
Live feasibility on real GPUs plus a 19-region replay: 50.9% modeled emissions cut.
Reserving for future calls finishes 10% more AI-agent workflows
Steering calls before connection lets more AI workflows finish on time without extra capacity.
· “ASGE-RR: Agentic Service Graph Embedding with Revisable Reservations for Dynamic AI-Agent Calls”
AutoThread cuts simulation runtime up to 83.8%
Worker-thread count follows the ratio of scheduling speed to task speed, guided by a neural operator and online tuning.
Open-source rig automates firmware power testing end to end
Firmware energy profiling and regression tests can run unattended on low-cost hardware.
· “An Open-Source Power Measurement Platform for System-Level Semiconductor Testing”
Ranker picks fastest GPU contraction plan 60% of the time
Structural plan features let a learned ranker top-3 the fastest plan in 96% of tested circuits.
· “Learning to Rank Tensor Network Contraction Plans for GPU-Accelerated Quantum Circuit Simulation”
Falcon-512 fits C-V2X, fails 90% delivery above lightest traffic
The only NIST post-quantum signature that fits today's sidelink spec delivers 90% only at lightest traffic, LOS.
Every M/PH2/1 queue has an exact formula
Queue lengths and sojourn times become two-term formulas, enabling exact sensitivity analysis and capacity sizing.
MFU predicts GPU power in LLM training within ~1% error
Per-GPU calibration with Model FLOPs Utilization lets simulators predict energy use without hardware counters.
· “Evaluating MFU as a Proxy for GPU Power for Energy-Aware Simulation of LLM Training”
