TileFuse introduces fused kernels and data layouts for W4A16/W8A16 on AMD XDNA2 NPUs, reporting up to 2.0x lower LLM prefilling latency and 64.6% lower energy versus baselines.
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TileFuse: A Fused Mixed-Precision Kernel Library for Efficient Quantized LLM Inference on AMD NPUs
TileFuse introduces fused kernels and data layouts for W4A16/W8A16 on AMD XDNA2 NPUs, reporting up to 2.0x lower LLM prefilling latency and 64.6% lower energy versus baselines.