Mixing a single low-noise logical circuit with several physical folded circuits in ZNE cuts the runtime needed for fixed estimator variance by orders of magnitude when the logical error-suppression factor γ≲0.1.
Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor
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Hybrid physical/logical zero-noise extrapolation with limited logical executions
Mixing a single low-noise logical circuit with several physical folded circuits in ZNE cuts the runtime needed for fixed estimator variance by orders of magnitude when the logical error-suppression factor γ≲0.1.