A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
Better Than Worst-Case Decoding for Quantum Error Correction
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A workload-aware surface-code architecture with ancilla-centric patches and T-gate-based floorplanning reduces required data tiles by up to 21% while maintaining near-optimal cycles per instruction and reaching 90% efficiency for 10 concurrent programs.
citing papers explorer
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A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
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Toward designing workload-aware Surface Code Architectures
A workload-aware surface-code architecture with ancilla-centric patches and T-gate-based floorplanning reduces required data tiles by up to 21% while maintaining near-optimal cycles per instruction and reaching 90% efficiency for 10 concurrent programs.