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arxiv: 2605.01035 · v1 · submitted 2026-05-01 · 🪐 quant-ph

A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

Daniel B\'ascones , Arshpreet Singh Maan , Valentin Savin , Francisco Garcia-Herrero This is my paper

Pith reviewed 2026-05-09 18:53 UTC · model grok-4.3

classification 🪐 quant-ph
keywords FPGA architecturequantum LDPC codesGARI methodmessage-passing decodingcorrelated errorsreal-time decodingresource reusebivariate bicycle code
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The pith

A resource-reusing FPGA architecture decodes correlated errors in any quantum LDPC code at 596 ns average latency while using one-sixth the resources of prior designs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a hardware decoder that runs message-passing inference on graphs modified by the GARI method to capture error correlations in quantum LDPC codes. The design reuses computational resources across a modest number of parallel cores so that the same circuit block can serve different codes without a full redesign. A working implementation on a VCU19P device with three cores for the [[144,12,12]] bivariate bicycle code reaches 596 ns per round and consumes six times fewer FPGA resources than the earlier GARI proposal. If the approach holds, quantum error-correction layers can place multiple accurate decoders on one classical chip while staying inside real-time and power budgets.

Core claim

The architecture implements message-passing decoding directly on the detector-error graph produced by GARI, augments that graph once per code, then reuses the same processing elements across rounds and across multiple cores; this yields a flexible, scalable decoder that maintains decoding accuracy for correlated errors, achieves an average latency of 596 ns per round on the [[144,12,12]] code, and reduces resource consumption by a factor of six relative to the previous GARI-based design, thereby enabling the first multi-core correlated-error decoder on a single FPGA.

What carries the argument

GARI-augmented graph for message-passing inference, which encodes detector correlations so that standard belief-propagation hardware can handle realistic error models while supporting resource reuse across cores.

If this is right

  • Multiple decoder cores can operate simultaneously on one FPGA device, raising throughput for larger quantum processors.
  • The same hardware block can be retargeted to new LDPC codes by changing only the graph wiring, reducing redesign effort.
  • Power and area of the classical control layer drop enough to allow denser integration with quantum hardware.
  • Real-time decoding latency stays below one microsecond even when handling correlated errors.
  • The architecture meets the scaling requirements for energy-conscious quantum error correction without accuracy trade-offs.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the reuse pattern continues to scale, the decoder could be placed on the same die as the quantum control electronics, shortening the feedback loop.
  • The method may apply to other sparse-graph codes that need correlation handling, such as certain surface-code variants.
  • Testing the design at higher core counts would reveal whether routing congestion eventually limits the claimed flexibility.
  • Lower classical power draw could extend the practical runtime of cryogenic quantum systems before heat-load limits are reached.

Load-bearing premise

The GARI graph structure preserves enough accuracy for message passing to work on correlated errors without extra hardware or loss of performance when resources are shared among cores.

What would settle it

Run the same three-core design on a second, structurally different quantum LDPC code, measure both its FPGA resource count and its logical error rate under a realistic correlated-noise model, and check whether resource savings and accuracy remain within the reported bounds.

Figures

Figures reproduced from arXiv: 2605.01035 by Arshpreet Singh Maan, Daniel B\'ascones, Francisco Garcia-Herrero, Valentin Savin.

Figure 1
Figure 1. Figure 1: Overview of the GARI architecture from this work. view at source ↗
Figure 2
Figure 2. Figure 2: The architecture for the DX, DZ decoder. Memory elements shown in blue (light for RAM, dark for ROM). I/O in purple. Sub-modules in gray. Output filtering is not required, since downstream processing is protected by the input stage, which blocks invalid values. Within the CNU, message updates are performed according to the normalized min-sum rules [28], exchanging information between all connected variable… view at source ↗
Figure 3
Figure 3. Figure 3: Architecture for the U, V decoder. Memory elements shown in blue (light for RAM, dark for ROM), I/O in purple. Sub-modules in gray. to simplify the hardware, since their messages are equal to the initial LLR value plus the incoming message from the opposite matrix update. • A single variable node from either e¯X or e¯Z, whose message must be brought in from the DX, DZ unit. Note that any processing order w… view at source ↗
Figure 4
Figure 4. Figure 4: The crossbar interconnect. Note that the inputs and outputs are view at source ↗
Figure 5
Figure 5. Figure 5: Architecture for the full decoder. Note the straightforward mapping between view at source ↗
Figure 7
Figure 7. Figure 7: Timing for the [[144, 12, 12]] gross code. plus a small overhead to fill the pipeline. In our experiments, eight pipeline stages are sufficient to achieve clock frequencies above 300 MHz. It is important to note that the separation between checks that share a variable must be greater than the number of pipeline stages to avoid using outdated (stale) values. In practice, for the [[144, 12, 12]] gross code, … view at source ↗
Figure 8
Figure 8. Figure 8: Placement of a single core of the proposed decoder for correlated view at source ↗
Figure 9
Figure 9. Figure 9: Placement of a three-decoder ensemble for correlated errors within the view at source ↗
read the original abstract

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The paper introduces a scalable FPGA architecture for real-time decoding of correlated errors in quantum LDPC codes, based on message-passing decoding of the detector error model produced by the GARI graph augmentation method. The design uses resource reuse with modest parallelism to reduce area and power while targeting low latency. As a case study, an ensemble of three decoder cores is implemented on a VCU19P FPGA for the [[144,12,12]] bivariate bicycle code, reporting an average latency of 596 ns per decoding round and six times fewer resources than the prior GARI-based proposal. The architecture is presented as adaptable in principle to arbitrary quantum LDPC codes via GARI, enabling energy-conscious scaling of the classical QEC layer without accuracy loss under correlated errors.

Significance. The concrete FPGA implementation with measured resource counts and latency provides practical data for hardware QEC, and the demonstration of multiple cores on a single device is a clear advance toward scalable classical control. If the accuracy-preservation claim holds, the work supports better power/area trade-offs for real-time decoding of correlated errors. The in-principle adaptability argument is a strength, though its significance depends on verification that GARI-augmented graphs remain efficiently decodable by message passing.

major comments (1)
  1. Abstract and case-study description: the central claim that the architecture operates 'without compromising decoding accuracy under correlated errors' is load-bearing yet unsupported by any error-rate curves, logical-error-rate comparisons against a non-GARI baseline, or details on how accuracy was verified for the [[144,12,12]] code. Without these data the performance claim cannot be assessed.
minor comments (2)
  1. The description of the resource-reuse strategy and three-core ensemble would benefit from an explicit diagram or table showing the mapping of GARI-augmented check nodes to FPGA resources.
  2. Clarify whether the reported 596 ns latency includes all pipeline stages or only the message-passing iterations; this affects direct comparison with other real-time decoders.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their detailed review and constructive feedback. We address the major comment point by point below.

read point-by-point responses

  1. Referee: Abstract and case-study description: the central claim that the architecture operates 'without compromising decoding accuracy under correlated errors' is load-bearing yet unsupported by any error-rate curves, logical-error-rate comparisons against a non-GARI baseline, or details on how accuracy was verified for the [[144,12,12]] code. Without these data the performance claim cannot be assessed.

    Authors: We thank the referee for highlighting this point. The architecture implements the exact message-passing procedure on the GARI-augmented detector error model with no algorithmic changes or approximations, so decoding accuracy is identical to the software GARI decoder. The original GARI publication already provides error-rate curves and logical-error-rate comparisons (including against non-augmented baselines) for the [[144,12,12]] bivariate bicycle code under correlated errors. During hardware development we performed bit-accurate and cycle-accurate simulations confirming that the FPGA output matches the software decoder on the same inputs. In the revised manuscript we will add a short paragraph in the case-study section that (i) explicitly references the relevant accuracy results from the GARI work and (ii) describes the equivalence verification steps performed for the FPGA implementation. We will also qualify the abstract claim to state that accuracy is preserved relative to the GARI software decoder. revision: yes

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper reports an FPGA implementation of a message-passing decoder that exploits the GARI-augmented graph structure for a specific bivariate bicycle code. All quantitative claims (596 ns average latency, six-fold resource reduction versus prior GARI proposal, three-core ensemble on VCU19P) are direct measurements from synthesis and timing analysis on the target device. No equations, fitted parameters, or predictions are defined in terms of the reported outcomes; the architecture description treats GARI as an external input framework rather than re-deriving or fitting its properties. The scaling and adaptability statements are scoped as design goals supported by the concrete case study, not as self-referential derivations.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on the assumption that the GARI rewiring produces a graph whose message-passing decoder remains accurate for the target correlated error model; no independent verification of that accuracy is supplied in the abstract. No free parameters or new invented entities are introduced in the abstract.

axioms (1)
  • domain assumption GARI-augmented graphs admit efficient message-passing decoding without accuracy degradation for the bivariate bicycle code under the detector error model.
    Invoked implicitly when the architecture is claimed to preserve decoding accuracy while exploiting the GARI structure.

pith-pipeline@v0.9.0 · 5510 in / 1373 out tokens · 33485 ms · 2026-05-09T18:53:34.979022+00:00 · methodology

discussion (0)

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