Union-find decoder for surface code achieves finite threshold under circuit-level stochastic errors with quasi-polylog parallel runtime bound.
arXiv preprint arXiv:2511.21660 , year=
6 Pith papers cite this work. Polarity classification is still indexing.
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quant-ph 6years
2026 6representative citing papers
Concatenating quantum Reed-Solomon outer codes over the gross code using Galois qudits reaches teraquop regime at 10^{-3} physical noise with lower overhead than prior two-gross-code constructions.
Forced-gap post-selection on bivariate bicycle codes and surgery gadgets improves logical error rates by a factor of more than 4 using Relay-BP decoding at fixed post-selection rate.
DART-Q shows that cached state organization, overload policies, and service capacity determine whether real-time QLDPC decoders can meet deadlines under finite memory and varying load.
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
citing papers explorer
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Proof of a finite threshold for the union-find decoder
Union-find decoder for surface code achieves finite threshold under circuit-level stochastic errors with quasi-polylog parallel runtime bound.
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Concatenating Algebraic Codes over High-Rate Quantum LDPC Codes
Concatenating quantum Reed-Solomon outer codes over the gross code using Galois qudits reaches teraquop regime at 10^{-3} physical noise with lower overhead than prior two-gross-code constructions.
-
Forced Gap Post-Selection for Quantum LDPC Codes and their Operations
Forced-gap post-selection on bivariate bicycle codes and surgery gadgets improves logical error rates by a factor of more than 4 using Relay-BP decoding at fixed post-selection rate.
-
DART-Q : A Deadline-Driven Framework for Real-Time QLDPC Decoding
DART-Q shows that cached state organization, overload policies, and service capacity determine whether real-time QLDPC decoders can meet deadlines under finite memory and varying load.
-
Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
-
A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.