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arxiv: 2411.10406 · v3 · pith:CG55KPMUnew · submitted 2024-11-15 · 🪐 quant-ph · cond-mat.dis-nn· cs.AI· cs.DC

How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits

Masoud Mohseni , Artur Scherer , K. Grace Johnson , Oded Wertheim , Matthew Otten , Namit Anand , Navid Anjum Aadit , Yuri Alexeev
show 43 more authors
Gilad Ben-Shach Kirk M. Bresniker Kerem Y. Camsari Barbara Chapman Soumitra Chatterjee Shuvro Chowdhury Gebremedhin A. Dagnew Tom Dvir Aniello Esposito Farah Fahim Michael Ferguson Marco Fiorentino Archit Gajjar Katerina Gratsea Gaurav Gyawali Christian Heiter Ali H. Z. Kavaki Abdullah Khalid Xiangzhou Kong Bohdan Kulchytskyy Elica Kyoseva Ruoyu Li P. Aaron Lott Igor L. Markov Robert F. McDermott Lucas Morais Giacomo Pedretti Pooja Rao Eleanor Rieffel Allyson Silva John Sorebo Panagiotis Spentzouris Ziv Steiner Boyan Torosov Davide Venturelli Robert J. Visser Zak Webb Xin Zhan Yonatan Cohen Pooya Ronagh Alan Ho Raymond G. Beausoleil John M. Martinis
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Pith reviewed 2026-05-18 22:36 UTC · model grok-4.3

classification 🪐 quant-ph cond-mat.dis-nncs.AIcs.DC
keywords quantum computingsuperconducting qubitssurface codeerror correctionquantum chemistryHPC integrationscalingresource estimation
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The pith

Scaling superconducting quantum computers from hundreds to millions of qubits requires semiconductor fabrication advances, surface-code error correction, and tight integration with classical high-performance computing.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper reviews the engineering steps needed to move quantum computation from small demonstrations to utility-scale systems that solve problems in chemistry and materials science. It models resource requirements for error-corrected superconducting qubits under realistic error distributions and shows how improvements in hardware quality plus close quantum-classical coupling can reduce the number of physical qubits and runtime by large factors. A reader cares because the analysis uses current semiconductor processes as the foundation, rather than assuming breakthroughs in entirely new qubit technologies. The estimates cover concrete applications such as molecular energy calculations, catalyst design, and Fermi-Hubbard models. The work also outlines custom accelerators for hybrid probabilistic computing tasks that mix quantum and classical resources.

Core claim

The central claim is that orders of magnitude better performance for utility-scale tasks can be reached by combining achievable improvements in superconducting qubit error rates and yields with systems-level integration to classical HPC, all while relying on surface-code error correction whose overhead is quantified under realistic error models.

What carries the argument

Surface-code error correction together with a resource and sensitivity analysis that maps current, target, and desired hardware specifications onto application runtimes and qubit counts.

Load-bearing premise

Target specifications for qubit error rates, coherence times, and fabrication yields can be met with existing semiconductor manufacturing methods and that surface-code performance follows the modeled behavior under realistic error distributions.

What would settle it

A measured logical error rate in a surface-code patch that fails to improve exponentially with code distance when physical error rates are held at the paper's target values would disprove the scalability projection.

read the original abstract

In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits. Nevertheless, there are significant outstanding challenges in quantum hardware, fabrication, software architecture, and algorithms on the path towards a full-stack scalable quantum computing technology. Here, we provide a comprehensive review of these scaling challenges. We show how to facilitate scaling by adopting existing semiconductor technology to build much higher-quality qubits, employing systems engineering approaches, and performing distributed heterogeneous quantum-classical computing. We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. We provide comprehensive resource estimates for several utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulation. We show that orders of magnitude enhancement in performance could be obtained by a combination of hardware improvements and tight quantum-HPC integration. Furthermore, we introduce high-performance architectures for quantum-probabilistic computing with custom-designed accelerators to tackle today's industry-scale classical optimization, machine learning, and quantum simulation tasks in a cost-effective manner.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 3 minor

Summary. The manuscript is a comprehensive review of scaling challenges for quantum computers from hundreds to millions of qubits, centered on superconducting qubits and surface-code error correction. It synthesizes hardware, fabrication, software, and algorithmic issues, then delivers detailed resource estimates and sensitivity analyses for utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulations. The central claim is that orders-of-magnitude performance gains are achievable through a combination of hardware improvements to target specifications and tight quantum-HPC integration, while also introducing high-performance architectures for quantum-probabilistic computing.

Significance. If the modeled error distributions and projected hardware targets hold, the paper supplies a useful quantitative roadmap and concrete resource counts that can inform experimental priorities in the field. The emphasis on systems engineering, heterogeneous integration, and sensitivity analysis under realistic error conditions strengthens its practical value for guiding development toward fault-tolerant systems.

minor comments (3)
  1. In the resource estimates for the Fermi-Hubbard simulation, the logical qubit overhead and runtime projections could include a short explicit statement of how the surface-code cycle time is derived from the physical gate times to improve traceability.
  2. The abstract introduces 'quantum-probabilistic computing' with custom accelerators; a brief clarifying sentence in the introduction linking this concept to the main scaling discussion would reduce potential reader confusion.
  3. Several tables listing current/target/desired specifications would benefit from an additional column or footnote referencing the specific external literature sources used for each parameter value.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for their positive and constructive assessment of our manuscript. The recommendation for minor revision is noted, and we will incorporate improvements to enhance clarity and completeness where appropriate.

Circularity Check

1 steps flagged

Minor self-citation in sensitivity parameters; central claims remain conditional on external assumptions

specific steps
  1. self citation load bearing [Abstract / resource and sensitivity analysis]
    "We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors."

    The current/target/desired specifications used as inputs to the sensitivity analysis and resource estimates are drawn from the authors' prior work and community consensus; this introduces moderate dependence on self-referenced assumptions for the quantitative performance projections, even though the projections themselves are framed as conditional.

full rationale

The paper is a review synthesizing scaling challenges and resource estimates for utility-scale applications under explicitly stated current/target/desired superconducting-qubit specifications and surface-code error models. These specifications are presented as open challenges rather than derived results. The sensitivity analysis draws parameters from prior literature (including some author-overlapping work), but this does not reduce the headline performance-enhancement claim to a self-referential fit or definition. No equation or derivation is shown to equal its own inputs by construction, and the argument structure relies on modeled external benchmarks.

Axiom & Free-Parameter Ledger

2 free parameters · 2 axioms · 0 invented entities

The central claims rest on standard assumptions from quantum error correction literature and projected hardware parameters that are treated as inputs rather than derived. No new entities are postulated.

free parameters (2)
  • target physical error rate per gate
    Used as input for surface-code resource estimates; values drawn from current and desired superconducting qubit specs without new derivation.
  • qubit coherence time targets
    Fitted to enable the claimed scaling; chosen to match semiconductor fabrication projections.
axioms (2)
  • domain assumption Surface code error correction thresholds and overheads follow established models under realistic error distributions.
    Invoked throughout the resource analysis sections without re-derivation.
  • domain assumption Semiconductor fabrication techniques can be directly adapted to produce higher-quality superconducting qubits at scale.
    Central premise for the hardware scaling strategy.

pith-pipeline@v0.9.0 · 6007 in / 1408 out tokens · 42162 ms · 2026-05-18T22:36:21.547519+00:00 · methodology

discussion (0)

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Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

  • Foundation.DimensionForcing dimension_forced unclear
    ?
    unclear

    Relation between the paper passage and the cited Recognition theorem.

    We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. We provide comprehensive resource estimates for several utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulation.

  • Foundation.HierarchyEmergence hierarchy_emergence_forces_phi unclear
    ?
    unclear

    Relation between the paper passage and the cited Recognition theorem.

    We show that orders of magnitude enhancement in performance could be obtained by a combination of hardware improvements and tight quantum-HPC integration.

What do these tags mean?
matches
The paper's claim is directly supported by a theorem in the formal canon.
supports
The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends
The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses
The paper appears to rely on the theorem as machinery.
contradicts
The paper's claim conflicts with a theorem or certificate in the canon.
unclear
Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Forward citations

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