Recognition: 2 theorem links
· Lean TheoremTour de gross: A modular quantum computer based on bivariate bicycle codes
Pith reviewed 2026-05-13 19:29 UTC · model grok-4.3
The pith
Bicycle architecture supports an order of magnitude larger logical quantum circuits than surface codes for the same number of physical qubits.
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
For two bivariate bicycle codes of distances 12 and 18, the authors construct a complete set of fault-tolerant logical instructions whose error rates are estimated under circuit noise, then supply a compilation method that respects the modular constraints, yielding resource estimates in which a given number of physical qubits supports roughly ten times as many logical operations as surface-code equivalents.
What carries the argument
Bivariate bicycle codes: a family of high-rate quantum LDPC codes whose modular embedding supplies the physical layout and whose distance properties underpin the fault-tolerant instruction set.
If this is right
- With fixed physical qubits, the architecture executes logical circuits whose size scales roughly ten times larger than surface-code implementations.
- The explicit instruction sets enable universal quantum computation while preserving the low-overhead properties of the underlying codes.
- Resource estimates already include the cost of compilation and inter-module operations, so further code or circuit improvements translate directly into additional gains.
- The modular design separates the code construction from the hardware connectivity, allowing independent advances in either domain.
Where Pith is reading between the lines
- Similar modular embeddings could be explored for other high-rate LDPC families to test whether the order-of-magnitude advantage generalizes.
- The compilation strategy may reduce the depth overhead that typically dominates large-scale algorithm costs, potentially lowering total runtime even before physical error rates improve.
- If the noise-model assumptions hold at scale, the approach could shift the qubit-count threshold at which useful fault-tolerant algorithms become feasible.
- Hardware layouts that already support dense local connectivity could adopt the bicycle tiling with minimal redesign.
Load-bearing premise
The codes keep their designed distance and logical error suppression when placed in the modular layout and operated with the proposed compilation and gate circuits.
What would settle it
A circuit-level simulation or experiment on the modular layout that measures logical error rates for the distance-12 or distance-18 code exceeding the paper's reported thresholds under the same noise model.
read the original abstract
We present the bicycle architecture, a modular quantum computing framework based on high-rate, low-overhead quantum LDPC codes identified in prior work. For two specific bivariate bicycle codes with distances 12 and 18, we construct explicit fault-tolerant logical instruction sets and estimate the logical error rate of the instructions under circuit noise. We develop a compilation strategy adapted to the constraints of the bicycle architecture, enabling large-scale universal quantum circuit execution. Integrating these components, we perform end-to-end resource estimates demonstrating that an order of magnitude larger logical circuits can be implemented with a given number of physical qubits on the bicycle architecture than on surface code architectures. We anticipate further improvements through advances in code constructions, circuit designs, and compilation techniques.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript presents the bicycle architecture, a modular quantum computing framework based on high-rate bivariate bicycle codes (quantum LDPC codes). For two explicit codes of distances 12 and 18, the authors construct fault-tolerant logical instruction sets, estimate logical error rates under a circuit-noise model, develop a modular compilation strategy, and perform end-to-end resource estimates claiming that an order of magnitude larger logical circuits can be executed with a fixed number of physical qubits compared to surface-code baselines.
Significance. If the results hold, the work is significant for demonstrating practical advantages of high-rate LDPC codes in modular hardware settings. The explicit instruction sets and numerical estimates under circuit noise provide concrete, falsifiable resource counts that could guide experimental implementations, addressing both overhead and connectivity challenges in scaling quantum computation beyond surface-code approaches.
major comments (3)
- [Compilation strategy] Compilation strategy section: The claim that the modular layout and inter-module operations preserve the distance and threshold of the distance-12/18 bivariate bicycle codes is not supported by explicit verification or simulation; the additional gates and connectivity constraints could introduce correlations that raise the effective logical error rate, directly undermining the order-of-magnitude scaling advantage reported in the resource estimates.
- [Logical error rate estimates] Logical error rate estimates (for d=12 and d=18 codes): The reported rates are obtained under a circuit-noise model that does not incorporate the modular compilation overhead factor; if this factor increases the logical error rate by even a modest amount, the end-to-end comparison to surface codes collapses, as the headline claim rests on these rates remaining unchanged.
- [End-to-end resource estimates] End-to-end resource estimates section: The order-of-magnitude improvement is derived from specific choices of physical error rate per gate and modular connectivity overhead; no sensitivity analysis is provided for variations in these free parameters, leaving the robustness of the scaling claim untested.
minor comments (2)
- [Abstract] The abstract refers to 'two specific bivariate bicycle codes' without naming their parameters or referencing the prior work; adding this detail would improve immediate clarity.
- Figures depicting the modular layout would benefit from clearer annotations distinguishing intra-module and inter-module connections to aid reader understanding of the compilation constraints.
Simulated Author's Rebuttal
We are grateful to the referee for their thorough review and valuable suggestions. We have carefully considered each major comment and provide point-by-point responses below, indicating where revisions will be made to strengthen the manuscript.
read point-by-point responses
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Referee: [Compilation strategy] Compilation strategy section: The claim that the modular layout and inter-module operations preserve the distance and threshold of the distance-12/18 bivariate bicycle codes is not supported by explicit verification or simulation; the additional gates and connectivity constraints could introduce correlations that raise the effective logical error rate, directly undermining the order-of-magnitude scaling advantage reported in the resource estimates.
Authors: We agree that explicit numerical verification of the full modular architecture under circuit noise would provide stronger support. However, the inter-module operations are constructed using lattice surgery techniques adapted to the bivariate bicycle code structure, which by design maintain the code distance as they involve only local measurements and corrections within the code's stabilizer framework. Potential correlations from connectivity are mitigated by the high-rate nature of the codes and the modular separation. In the revised manuscript, we will include a more detailed theoretical argument and a small-scale simulation for a subset of operations to bound the impact on the logical error rate. revision: partial
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Referee: [Logical error rate estimates] Logical error rate estimates (for d=12 and d=18 codes): The reported rates are obtained under a circuit-noise model that does not incorporate the modular compilation overhead factor; if this factor increases the logical error rate by even a modest amount, the end-to-end comparison to surface codes collapses, as the headline claim rests on these rates remaining unchanged.
Authors: The logical error rates reported are for the individual logical instructions as implemented in the code, under the standard circuit noise model. The modular compilation strategy incorporates the overhead by counting the total number of physical operations required, which is already factored into the resource estimates. We will revise the text to explicitly state that the effective logical error rate per instruction includes an estimated overhead multiplier derived from the compilation, and provide the calculation details to show that the rates remain sufficiently below the threshold for the claimed advantage to hold. revision: partial
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Referee: [End-to-end resource estimates] End-to-end resource estimates section: The order-of-magnitude improvement is derived from specific choices of physical error rate per gate and modular connectivity overhead; no sensitivity analysis is provided for variations in these free parameters, leaving the robustness of the scaling claim untested.
Authors: We selected physical error rates (e.g., 10^{-3}) and overhead factors based on near-term experimental projections. To address this, we will add a sensitivity analysis in the revised version, including plots showing the logical circuit volume advantage as a function of physical error rate and connectivity overhead, demonstrating that the order-of-magnitude improvement persists over a range of plausible parameters. revision: yes
Circularity Check
No circularity: resource estimates follow from explicit constructions and simulations
full rationale
The paper constructs explicit fault-tolerant logical instruction sets for the bivariate bicycle codes, estimates their logical error rates under a stated circuit-noise model via simulation, develops a modular compilation strategy, and integrates the resulting quantities into end-to-end resource counts. These steps are computational and constructive; they do not reduce any claimed prediction to a fitted parameter renamed as output, nor does any load-bearing premise rest solely on a self-citation whose content is itself unverified. The order-of-magnitude comparison to surface-code baselines is obtained by plugging the simulated rates and overheads into standard resource formulas, which are independent of the bicycle architecture itself. No equation or claim is shown to be definitionally equivalent to its inputs.
Axiom & Free-Parameter Ledger
free parameters (2)
- physical error rate per gate
- modular connectivity overhead factor
axioms (1)
- domain assumption Bivariate bicycle codes achieve the claimed distances and thresholds under circuit noise when implemented with the proposed gates.
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Automatically from the construction in Eq
¯X1 and ¯Z1 anti-commute and ¯X7 and ¯Z7 anticommute. Automatically from the construction in Eq. (31), all other pairs of Paulis in that equation commute
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[10]
(31) and their shifts generate the entire 12-qubit logical Pauli group
The operators in Eq. (31) and their shifts generate the entire 12-qubit logical Pauli group
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[11]
(31) commute, they do not overlap
If two different operators in Eq. (31) commute, they do not overlap. If two operators anticom- mute, they overlap on exactly one qubit
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[12]
The set ofZ-checks that overlap with¯X1 is disjoint from the set ofZ-checks that overlap with ¯X7. Likewise, the set ofX-checks that overlap with¯Z1 is disjoint from the set ofX-checks that overlap with ¯Z7. These properties ensure that the logical processing unit (LPU) that we create with qLDPC surgery and attach to the orignal BB code is both sufficient...
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[13]
Initialize all edge qubits in|0⟩
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[14]
Measure all checks of the LPU. By the stabilizer update rules [Got97], this deforms the original code so that some of its checks gain support on edge qubits. Measure all the checks of this deformed code as well. The logical measurement result is¯m =Q v∈V mv where mv = ±1 are the results of measuring the vertex checks. Repeat this step a total ofC times to...
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[15]
Let me = ±1 be the result of measuring edge qubite
Return to the original code by measuring the checks of the original code and measuring all edge qubits in theZ basis. Let me = ±1 be the result of measuring edge qubite
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[16]
Correct the original code by a Pauli operator. To describe the correction, fix an arbitrary vertex v0 ∈ V . For any other vertexv, let µv be an arbitrary path fromv0 to v. If Q e∈µv me = −1 apply a correction ofLq to each qubitq in the original code on which checkv had support. After these steps, it can be shown that the logical projector(I + ¯mL)/2 has b...
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[17]
Bell states are initialized on(γ, ˜γ) ∈ C Bell
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[18]
Edges with γ in the LPU andδ in the BB code are performed
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[19]
Edges contained entirely in the BB code are scheduled according to the standard syndrome cycle presented in [Bra+24]
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[20]
We find an optimal edge-coloring of this bipartite graph using the ‘gcol’ python package
Edges contained entirely in the LPU are scheduled in two phases: (a) We consider the subgraph of edgesγ ∼ δ where γ acts as anX-check. We find an optimal edge-coloring of this bipartite graph using the ‘gcol’ python package. We then associate edges with the same color to layers in the circuit. (b) We do the same for edges withγ acting as aZ-check. 16It is...
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[21]
Edges with δ in the LPU andγ in the BB code are performed. Once the order of the gates has been determined as above, the gates are scheduled as early as possible while meeting the constraint Eq. (67). We find that the subcircuit obtained from the graph coloringoftheLPUedgesdominatesthecircuitdepth, andalsoremovestheopportunityforsubsequent cycles to overl...
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[22]
A fault e produces syndrome σ = He
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[23]
The decoder D returns a correctionc = D(σ) satisfying Hc = σ
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[24]
Correction succeeds ifAc = Ae, and fails otherwise. Successful correction in the third step is typically facilitated by choosing a highly probable (in the physical noise model) errore′ consistent with syndromeσ = He = He ′ as the correctionc = e′ in the second step. Finding the most probable correction is generically hard [IP15], but heuristic decoders, l...
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[25]
d∗ s, the code distance of the deformed code, and
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[26]
We reduce both tasks to the same optimization problem
d∗ t, the minimum weight of a Pauli operator that both commutes with all checks of the deformed code (minus the vertex checks), but anticommutes with the operator we are measuring. We reduce both tasks to the same optimization problem. Let Pn be the entire Pauli group on some fixed number of qubitsn, M be a set of Pauli operators, and q be a particular Pa...
work page 2016
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[27]
such that the surface code architecture has circuit failure probability less than1 3. We make similar assumptions to those described in [Bev+22], namely that each patch requires 2d2 physical qubits, that P1 = 0 .03 p 0.01 d/2 predicts the per-cycle error rate of each surface code patch [Fow+12; WFH11], and that an arbitrary multi-qubit logical Pauli measu...
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[28]
The standard deviation is visually indistinguishable, so is not plotted. For larger numbers of T gates, we extrapolate using a linear fit (dashed) whose intersection with1 3 is given in Figure 10a. for one Pauli-generated rotation in C) can be implemented in d QEC cycles, using about half the patches for routing. For simplicity, we assume a single T facto...
discussion (0)
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