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arxiv: 2604.19735 · v1 · submitted 2026-04-21 · 🪐 quant-ph

Recognition: unknown

Architecting Early Fault Tolerant Neutral Atoms Systems with Quantum Advantage

Sahil Khan , Sayam Sethi , Kaavya Sahay , Yingjia Lin , Jude Alnas , Suhas Kurapati , Abhinav Anand , Jonathan M. Baker
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Kenneth R. Brown
Authors on Pith no claims yet

Pith reviewed 2026-05-10 02:48 UTC · model grok-4.3

classification 🪐 quant-ph
keywords neutral atomsfault-tolerant quantum computingquantum advantageteleportationquantum error correctionspacetime costearly fault tolerancelogical gates
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The pith

A teleportation-based scheme for neutral-atom systems delivers up to 3x speedup in fault-tolerant logical operations at fixed space cost.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that neutral-atom platforms can support early fault-tolerant quantum computation for tasks like dynamics simulation by replacing serial extractor methods with parallelized logical gates. Reconfigurable connectivity is used to teleport data and run operations simultaneously in unused space rather than executing them one after another. Detailed simulations that include shuttling schedules, gate compilation, and probabilistic resource-state preparation show that the resulting spacetime volume is lower than competing architectures. A sympathetic reader would care because the work supplies concrete atom counts and wall-clock times at which quantum advantage becomes plausible.

Core claim

The authors introduce a teleportation-based parallelization scheme for logical gates on neutral atoms. This scheme achieves up to approximately 3 times speedup over extractor architectures at identical space cost and records the lowest spacetime cost among viable architectures before external resource states are counted. Full compilation simulations that incorporate shuttling patterns, gate scheduling, and resource-state nondeterminism confirm that the speedups persist and that quantum advantage benchmarks can be completed with 11,495 atoms in roughly 15 hours.

What carries the argument

The teleportation-based scheme that exploits reconfigurable neutral-atom connectivity to execute logical operations in parallel rather than serially.

If this is right

  • Quantum advantage simulations become feasible with 11,495 atoms and a 15-hour runtime.
  • Spacetime cost is minimized among extractor, serial, and other parallel schemes before resource-state overhead is added.
  • Success probabilities and exact resource counts are obtained from full gate-level scheduling.
  • The same parallelization applies to any neutral-atom error-correcting code that admits transversal or extractor gates.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Hardware that can rapidly reconfigure atom positions and perform fast teleportation will reach the reported advantage threshold sooner than platforms limited to fixed connectivity.
  • If resource-state generation is slower or noisier than modeled, the required atom count will rise above 11,495 while the 15-hour bound will lengthen.
  • The approach suggests that future neutral-atom arrays should be sized and zoned with explicit space left for parallel teleportation rather than packed at maximum density.

Load-bearing premise

The low-level compilation simulation that includes shuttling patterns and resource-state nondeterminism captures every real hardware overhead.

What would settle it

Implementation of the proposed architecture on an actual neutral-atom device that measures whether the end-to-end runtime for the quantum-advantage benchmark stays within the simulated 15 hours or exceeds it due to unaccounted costs.

Figures

Figures reproduced from arXiv: 2604.19735 by Abhinav Anand, Jonathan M. Baker, Jude Alnas, Kaavya Sahay, Kenneth R. Brown, Sahil Khan, Sayam Sethi, Suhas Kurapati, Yingjia Lin.

Figure 1
Figure 1. Figure 1: a) Hybrid architectures with low spatial requirements suffer from severe thrashing, where the load/store times increase wall time beyond the space efficient extractor. Once the equivalent time bounds are met, these architectures are too spatially demanding. b) A transversal architecture performs poorly in terms of time and space on serial-synthesis workloads due to the extra Clifford operations (blue) and … view at source ↗
Figure 2
Figure 2. Figure 2: (a) Illustration of the quantum circuit considered in this work. (b) Corresponding compiled Pauli-based comput￾ing (PBC) instruction. (c) A transversal CNOT gate between two logical qubits encoded in the surface code that can be used to implement the circuit shown in (a). (d) Compiled PBC instruction (b) mapped onto the gross code architecture. For further details on the compilation procedure to transversa… view at source ↗
Figure 3
Figure 3. Figure 3: (a) A simple hybrid compilation policy that dele￾gates all computation to the surface code. This policy per￾forms a compute region store in parallel in step 1, as well as performing a T-state injection after loading in step 2. (b) A hybrid compilation policy that builds off (a) and allows for in-memory compute on single qubit gates of modules, gaining additional parallelism but taking the entire module off… view at source ↗
Figure 4
Figure 4. Figure 4: We detail our teleportation scheme to parallelize T￾state injection for the largest synthesis length at a time, found by cost 𝜏 (𝑅𝑧(𝜃)𝑖). On the left, we show the circuit where a given layer consists of 𝑅(𝜑) rotations, and an appropriate injection pivot identified arbitrarily once per each 𝑅(𝜑), we label 𝑎0, and 𝑏0. The T states are created by 𝑂(𝑀) T factories with magic states labeled |𝑚0⟩. The paralleliz… view at source ↗
Figure 5
Figure 5. Figure 5: Across the three QA benchmarks where our paral￾lel injection is allowed to parallelize, we see an increase in the number of modules utilized 3.1.1 Observation 1: R(𝜑) synthesis is the Main Bot￾tleneck. For our base assumption of 𝜖 = 10−10, synthesis takes nearly ∼ 100 T gates, translating to 100 non-Clifford injections and thus 100 timesteps. Meanwhile the maximum number of extractor instructions is 24 [56… view at source ↗
Figure 7
Figure 7. Figure 7: Total spacetime volume required by various hybrid compilers on the QASMBench benchmark suite (H1,H2,H3, as detailed in Section 4.3). We compare against the base extractor architecture Tour de Gross (TdG) [61], and our parallelized injection scheme (Section 3) 1. R(𝜑) synthesis comprises the majority of the circuit. In some QASMBench benchmarks [29], like the adder and multiplier, R(𝜑) rotations are trivial… view at source ↗
Figure 6
Figure 6. Figure 6: Total timesteps required by various hybrid compil￾ers on the QASMBench benchmark suite (H1,H2,H3, as de￾tailed in Section 4.3). We compare against the base extractor architecture Tour de Gross (TdG) [61], and our parallelized injection scheme (Section 3) 4.2 Transversal Architectures are Suboptimal in Spacetime Transversal implementations allow application level gate operations to be realized directly as l… view at source ↗
Figure 8
Figure 8. Figure 8: Four quantum advantage benchmarks and the relative performance of all three hybrid policies with idealized T state production, the baseline extractor Tour de Gross architecture, and our parallelized injection extractor scheme (Section 3). The benchmarks shown are: 2D Heisenberg Hamiltonian, 2D long-range transverse field Ising model, 2D nearest neighbor Ising model, and the Fermi-Hubbard model [PITH_FULL_… view at source ↗
Figure 10
Figure 10. Figure 10: Sensitivity to different hybrid code configurations of high-rate code as memory with a transversal admitting topological code: Hypergraph Product Simplex (HGPS) code + Surface code (SC), Bivariate Bicycle code (BB) + Color code (CC), and Lifted Product (LP) code + Surface code (SC). We report the total spacetime volume for each configuration. realistic T-factory constraints. We leverage the recent cultiva… view at source ↗
Figure 11
Figure 11. Figure 11: Four quantum advantage benchmarks and the spacetime performance of all three hybrid policies with idealized T state production, the baseline extractor Tour de Gross architecture, and our parallelized injection extractor scheme (Section 3). The benchmarks shown are: 2D Heisenberg Hamiltonian, 2D long-range transverse field Ising model, 2D nearest neighbor Ising model, and the Fermi-Hubbard model. injection… view at source ↗
Figure 12
Figure 12. Figure 12: Accounting for cultivation T throughput, the performance of our injection scheme and the base tour de gross compilation scheme is shown. The benchmarks are as follows: 2D Heisenberg Hamiltonian, 2D long range transverse field Ising model, 2D nearest neighbor transverse field Ising model, and the Fermi Hubbard model [PITH_FULL_IMAGE:figures/full_fig_p012_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: (a) A module is shown decomposed into its lower physical qubits by type. The mixed BB and LPU mapping is shown in pink depicting different left or right data qubits, or X/Z/Vertex/Cycle checks. Adapter checks are shown in the light blue (b) the maximum interaction distance 𝛿 is kept low with the mapping and adapter checks can shuttle in a translationally symmetric fashion such that inter-module measuremen… view at source ↗
read the original abstract

Recent advancements in neutral atom platforms have enabled exploration of early fault-tolerant (FT) architectures for applications with quantum advantage, such as quantum dynamics simulations. An efficient fault-tolerant architecture has both spatially efficient quantum error correction codes (low qubit overhead), and efficient methodologies (transversal based gates, extractor based gates, etc.) for logical computation, to minimize overall execution time. Achieving the right balance between space and time can be critical for enabling early FT demonstrations of quantum advantage. In this work, we identify bottlenecks in existing spatially efficient schemes, which tend to be very serial, and do not take advantage of unutilized space. We introduce a teleportation-based scheme that leverages the reconfigurable connectivity of neutral atoms to parallelize logical operations. Our approach achieves up to \textbf{$\mathbf{\sim 3 \times}$ speedup} over extractor architectures at no extra space cost and achieves the best spacetime performance among other viable architectures before accounting for external \textit{resource-states}. To rigorously evaluate performance, we construct explicit quantum advantage benchmarks and \textit{simulate} compilation to a fault-tolerant instruction set, including low-level gate scheduling and shuttling patterns, and resource-state nondeterminism. We find that our speedups still apply and report exact space-time cost along with success probabilities, identifying architectures capable of achieving quantum advantage \textbf{with as little as $\mathbf{11,495}$ atoms and a runtime of $\mathbf{\sim 15}$ hours}.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes a teleportation-based parallelization scheme for logical operations in early fault-tolerant neutral-atom quantum computing, exploiting reconfigurable connectivity to address serial bottlenecks in existing spatially efficient architectures such as extractors. Through explicit compilation simulations of quantum dynamics benchmarks that incorporate gate scheduling, shuttling patterns, and resource-state nondeterminism, the work claims up to ~3× speedup over extractor architectures at no extra space cost, the best spacetime performance among viable options, and concrete resource requirements for quantum advantage of as little as 11,495 atoms with a runtime of ~15 hours.

Significance. If the simulation results are robust, the manuscript supplies concrete, reproducible resource estimates and a new architecture that improves time performance for neutral-atom FTQC without space penalty, advancing feasibility assessments for early quantum advantage in dynamics simulations. The explicit low-level simulations with nondeterminism and shuttling are a clear strength, offering falsifiable performance numbers rather than abstract bounds.

major comments (2)
  1. [§4 and §5] §4 (Compilation Simulation) and §5 (Results): The central claims of ~3× speedup, best spacetime volume, and the specific numbers (11,495 atoms, ~15 h) are derived entirely from the low-level compilation simulation. The error model for shuttling and teleportation-based parallelization is not validated against independent simulators, hardware data, or sensitivity analysis, so unmodeled per-shuttle overheads or loss probabilities could directly inflate runtime and erase the reported advantage over extractor architectures.
  2. [§3 and §5.1] §3 (Benchmarks) and §5.1: The quantum advantage benchmarks are explicitly constructed, yet the paper provides no cross-check that the chosen dynamics simulations are representative enough to support the general claim of 'best spacetime performance among other viable architectures'; a single benchmark family risks overfitting the architecture comparison.
minor comments (2)
  1. [Abstract] Abstract: Bold formatting on numerical claims is nonstandard and reduces readability; plain text or italics would suffice.
  2. [§2] §2 (Architecture Description): The definition of the teleportation-based instruction set could include a small table summarizing gate costs, fidelities, and nondeterminism probabilities for direct comparison with extractor gates.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for their constructive report and positive assessment of the work's significance. We address each major comment below, indicating planned revisions where appropriate.

read point-by-point responses

  1. Referee: [§4 and §5] §4 (Compilation Simulation) and §5 (Results): The central claims of ~3× speedup, best spacetime volume, and the specific numbers (11,495 atoms, ~15 h) are derived entirely from the low-level compilation simulation. The error model for shuttling and teleportation-based parallelization is not validated against independent simulators, hardware data, or sensitivity analysis, so unmodeled per-shuttle overheads or loss probabilities could directly inflate runtime and erase the reported advantage over extractor architectures.

    Authors: We acknowledge that our error model relies on standard physical parameters drawn from the neutral-atom literature rather than direct validation against independent simulators or hardware data (the latter being unavailable at the required scale and fidelity). The model does incorporate nondeterminism for resource-state generation as detailed in §4. To address the concern, we will add an explicit sensitivity analysis in the revised §5 varying shuttle overheads and loss rates by factors of 2–5, showing that the reported speedup and spacetime advantage remain robust under these variations. We maintain that the core parallelization benefit is not erased even under conservative overhead assumptions. revision: partial

  2. Referee: [§3 and §5.1] §3 (Benchmarks) and §5.1: The quantum advantage benchmarks are explicitly constructed, yet the paper provides no cross-check that the chosen dynamics simulations are representative enough to support the general claim of 'best spacetime performance among other viable architectures'; a single benchmark family risks overfitting the architecture comparison.

    Authors: The selected benchmarks are standard examples of quantum dynamics simulations under local Hamiltonians, which constitute a primary target application class for early fault-tolerant neutral-atom systems. The architectural advantage derives from general parallelization enabled by reconfigurable connectivity and is not tuned to the specific dynamics. Nevertheless, we agree that additional cross-checks would strengthen the generality claim. In the revision we will expand §3 with a short justification of representativeness for the dynamics class and include results from one additional benchmark (e.g., a different interaction graph) to verify that the spacetime ordering versus extractor and other architectures is preserved. revision: yes

standing simulated objections not resolved
  • Direct validation of the shuttling and teleportation error model against experimental hardware data, as neutral-atom platforms have not yet reached the scale and fidelity needed for these fault-tolerant operations.

Circularity Check

0 steps flagged

No circularity; resource estimates from forward simulation of benchmarks

full rationale

The paper obtains its central claims (~3× speedup over extractor architectures, best spacetime performance, 11,495 atoms, ~15 h runtime) by constructing explicit quantum advantage benchmarks and simulating compilation to a fault-tolerant instruction set that includes low-level gate scheduling, shuttling patterns, and resource-state nondeterminism. This is forward modeling from concrete inputs rather than any reduction of the reported quantities to quantities defined by the architecture choice itself. No self-definitional steps, fitted inputs renamed as predictions, load-bearing self-citations, uniqueness theorems, or smuggled ansatzes appear in the derivation chain. The simulation outputs serve as independent evidence for the speedup and resource numbers.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The abstract supplies insufficient detail to enumerate all free parameters or axioms; the central claims rest on standard neutral-atom hardware assumptions and error-correction principles whose precise numerical values are not stated.

axioms (1)
  • domain assumption Neutral-atom platforms provide reconfigurable connectivity via atom shuttling that can be used for efficient teleportation of logical information.
    This assumption is required for the parallelization speedup to materialize at no extra space cost.

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Forward citations

Cited by 1 Pith paper

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    quant-ph 2026-04 unverdicted novelty 6.0

    INJEQT reduces synthillation error by up to 22x, wall-clock time by 13x, and space-time cost by 7.2x in extractor FTQC architectures via auxiliary Rz synthesis and pre-fetching.

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