A hot-zone architecture for OQFT on reconfigurable neutral-atom hardware yields tunable latency via 2-4 zones, converging to roughly 500 extra logical ancillae and 128-qubit peak parallelism for half-time performance on 256-2048 bit instances.
Spacetime- efficient and hardware-compatible complex quantum logic units in qldpc codes
6 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
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A microarchitecture-aware compiler for lattice surgery that exploits C-Phase commutativity to enable concurrent multi-target operations and dynamic event-driven scheduling, cutting execution time by up to 59.7 times versus standard baselines.
The [[144,12,12]] bivariate bicycle code is distributed across 4 to 12 processors in a star network, with simulations showing logical error rates under varying nonlocal noise scaling.
CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical error rates over surface codes.
A teleportation-based parallelization architecture for neutral-atom quantum error correction delivers up to 3x speedup over extractor methods at fixed space cost and enables simulated quantum advantage at 11,495 atoms and 15-hour runtime.
Adaptive-window decoding that shrinks or expands based on decoder confidence cuts reaction-time overhead in quantum error correction without raising logical error rates.
citing papers explorer
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Towards Deploying Optimistic Quantum Fourier Transforms: An Architecture-Algorithm Co-Design Study
A hot-zone architecture for OQFT on reconfigurable neutral-atom hardware yields tunable latency via 2-4 zones, converging to roughly 500 extra logical ancillae and 128-qubit peak parallelism for half-time performance on 256-2048 bit instances.
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C-Phase-Aware Compilation for Efficient Fault-Tolerant Quantum Execution
A microarchitecture-aware compiler for lattice surgery that exploits C-Phase commutativity to enable concurrent multi-target operations and dynamic event-driven scheduling, cutting execution time by up to 59.7 times versus standard baselines.
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Distributed Quantum Error Correction with Bivariate Bicycle Codes in a Modular Architecture
The [[144,12,12]] bivariate bicycle code is distributed across 4 to 12 processors in a star network, with simulations showing logical error rates under varying nonlocal noise scaling.
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CAbLECAR: efficiently scheduling QLDPC codes on a tileable spin qubit chip with shuttling
CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical error rates over surface codes.
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Architecting Early Fault Tolerant Neutral Atoms Systems with Quantum Advantage
A teleportation-based parallelization architecture for neutral-atom quantum error correction delivers up to 3x speedup over extractor methods at fixed space cost and enables simulated quantum advantage at 11,495 atoms and 15-hour runtime.
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ADaPT: Adaptive-window Decoding for Practical fault-Tolerance
Adaptive-window decoding that shrinks or expands based on decoder confidence cuts reaction-time overhead in quantum error correction without raising logical error rates.