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The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes
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The realisation of utility-scale quantum computing inextricably depends on the design of practical, low-overhead fault-tolerant architectures. We introduce the Pinnacle Architecture, which uses quantum low-density parity check (QLDPC) codes to allow for universal, fault-tolerant quantum computation with a spacetime overhead significantly smaller than that of any competing architecture. With this architecture, we show that 2048-bit RSA integers can be factored with fewer than one hundred thousand physical qubits, given a physical error rate of $10^{-3}$, code cycle time of $1$ microsecond and a reaction time of $10$ microseconds. We thereby demonstrate the feasibility of utility-scale quantum computing with an order of magnitude fewer physical qubits than has previously been believed necessary.
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Reference graph
Works this paper leans on
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Memory The architecture can also include memory. This is op- tional, but it is useful in cases where a large number of logi- cal qubits must be stored but not processed. It consists ofν code blocks of an Jnm, km, dmK quantum error-correcting code encoding µ=νk m logical qubits. Since these log- ical qubits are not processed, full processing blocks are not...
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[2]
Serial Operation As a baseline, let us first consider a serial mode of op- eration. In this mode, there is a single processing unit with κ logical qubits (and, for simplicity, we assume there is no memory). During each logical cycle, a joint logical Pauli measurement is performed on the processing unit and magic engine. In parallel, the magic engine produ...
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[3]
Fully Parallel Operation As a next step, we can consider the case of implement- ing a circuit that can be completely separated out into two or more independent circuits. In this context, we can separate the architecture up into a separate process- ing unit for each independent circuit and perform all the circuits in parallel. This reduces the number of lo...
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Flexibly Parallel Operation More common and general is the case where a circuit can be implemented partially in parallel. In such a circuit, no subset of logical qubits is entirely separable from the rest, but significant parts of the circuit involve operations on disjoint registers of logical qubits. A conventional circuit implementation would allow such...
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Recall that each processing unit accesses memory via a port
General Operation The final step to our fully general operation is to option- ally incorporate the memory. Recall that each processing unit accesses memory via a port. We allow for read-only memory access, which requires only gates that act as a con- trol on the port and a target on the processing unit [8, 35]. This means that the access can be provided b...
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[6]
Processing Units Using β processing blocks constructed from the GB code family introduced above (for any β∈N ), we can encode κ=βk logical qubits in βnpb physical qubits. Specifically, with a code distance of d= 16 , we can encode 14β logical qubits in 860β physical qubits. For better protection, we can instead use a code distance of d= 24 and encode 16β ...
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[7]
Magic Engines We construct each magic engine from code blocks of the same GB code family as those used for the processing blocks. These blocks naturally have the required L and R logical sectors, with k/2>5 logical qubits in each sector whend≥10. We use 15-to-1 magic state distillation on these code blocks to produce encoded | ¯T⟩ magic states [44]. Follo...
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For simplicity, we match the window size with the number of logical qubits in a logical sector, k/2
Memory For the memory, we use the same code blocks as are used for the processing blocks. For simplicity, we match the window size with the number of logical qubits in a logical sector, k/2. Each port then corresponds to one of the Z- type gadgets used in the gadget system of the processing blocks, along with a bridge to connect to a processing unit. The ...
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Algorithm The two-dimensional Fermi-Hubbard model represents a system of interacting fermions and has the Hamiltonian H=H h +H I = X ⟨i,j⟩ X σ∈{↑,↓} a† i,σaj,σ +a † j,σai,σ +u X i ˆni,↑ˆni,↓. (14) Here, i denotes the sites of an L×L lattice, ⟨i, j⟩ denotes pairs of nearest neighbours on this lattice, σ∈ {↑,↓} denotes spins states, a† and a represent creat...
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Implementation and Results Concretely, we consider the case of even L≤32 and u= 4 . In this regime, N≤2050 and we find numerically that the number of logical cycles satisfies T= 8×10 6, which also upper bounds theT count. This implies that the logical spacetime volume satisfies NT ≤2×10 10. Hence, the algorithm can be implemented with negligible failure p...
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[ 8], which uses techniques de- veloped by Ekerå and Håstad [58] and by Chevignard et al
Algorithm The algorithm we use is a generalisation of that pre- sented by Gidney in Ref. [ 8], which uses techniques de- veloped by Ekerå and Håstad [58] and by Chevignard et al. [59]. We refer to this algorithm as Gidney’s algorithm. This algorithm uses residue number system arithmetic to replace modular arithmetic over NRSA (the number being factored) w...
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These processing units can run in parallel throughout most of the computation
Implementation on Pinnacle Architecture To implement the algorithm on the Pinnacle Architec- ture, we begin by allocating a processing unit for each working register. These processing units can run in parallel throughout most of the computation. The only exception is the relatively short periods when the accumulators of the working registers are being agg...
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Physical Qubits:We now determine the number of physical qubits required
Resource Analysis a. Physical Qubits:We now determine the number of physical qubits required. Each working register corre- sponds to a processing unit with κ(f, ℓ, m) logical qubits, as given in Eq. (23), along with a magic engine. The num- ber of physical qubits required for the ρ working registers is therefore nw =ρ npb κ(f, ℓ, m) k +n me ! .(24) Each m...
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Results We now consider the resources—both physical qubits and time—required to factor an RSA-2048 integer on the instantiation of the Pinnacle architecture presented in Sec- tion V, given different hardware parameters, namely the code cycle time and physical error rate. Following Ref. [8], we expect the required logical error rate per logical qubit per l...
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