Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
Fault-tolerant logical measurements via homological measurement,
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Tricycle codes generalize bicycle codes to three homological dimensions, enabling constant-depth CCZ circuits and single-shot magic state generation with circuit-level thresholds above 0.5% and low error rates at block lengths of 50-100 qubits.
Wire codes are a construction that converts any stabilizer code into a local weight-3 subsystem code on an arbitrary graph via low-density Tanner-graph embedding, with overhead governed by the embedding quality.
Shor's algorithm for cryptographically relevant problems becomes feasible on neutral-atom systems with as few as 10,000 reconfigurable physical qubits via high-rate quantum error correction.
Two new heuristics reduce hardware-limited depth of commuting PPR groups by 10-20% on average (up to 50%) in QASMBench circuits compiled to PPRs.
citing papers explorer
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The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes
Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
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Magic tricycles: Efficient magic state generation with finite block-length quantum LDPC codes
Tricycle codes generalize bicycle codes to three homological dimensions, enabling constant-depth CCZ circuits and single-shot magic state generation with circuit-level thresholds above 0.5% and low error rates at block lengths of 50-100 qubits.
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Wire Codes
Wire codes are a construction that converts any stabilizer code into a local weight-3 subsystem code on an arbitrary graph via low-density Tanner-graph embedding, with overhead governed by the embedding quality.
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Shor's algorithm is possible with as few as 10,000 reconfigurable atomic qubits
Shor's algorithm for cryptographically relevant problems becomes feasible on neutral-atom systems with as few as 10,000 reconfigurable physical qubits via high-rate quantum error correction.
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Optimizing Parallel Execution of Commuting Pauli Product Rotations
Two new heuristics reduce hardware-limited depth of commuting PPR groups by 10-20% on average (up to 50%) in QASMBench circuits compiled to PPRs.