Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
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UNVERDICTED 14representative citing papers
A new code surgery protocol measures t logically disjoint Pauli products on any LDPC code using O(t ω (log t + log³ω)) ancillas in O(d) time while preserving LDPC property and fault distance.
INJEQT reduces synthillation error by up to 22x, wall-clock time by 13x, and space-time cost by 7.2x in extractor FTQC architectures via auxiliary Rz synthesis and pre-fetching.
CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical error rates over surface codes.
Syn@fac optimization reduces estimated circuit failure probability by a factor of 9 on average across non-Clifford benchmarks for bivariate bicycle code modular FTQC architectures, with additional gains from transvection deferral and Clifford insertion.
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
A family of quantum LDPC codes with encoding rates exceeding 1/2 achieves logical error rates of 10^{-13} per round on atom arrays under 0.1% circuit noise using hierarchical decoding.
Shor's algorithm for cryptographically relevant problems becomes feasible on neutral-atom systems with as few as 10,000 reconfigurable physical qubits via high-rate quantum error correction.
A new scheme for fault-tolerant quantum computation on qLDPC codes achieves constant qubit overhead and time overhead O(d^{1+o(1)}) for good codes, faster than prior code surgery methods for a<2.
Neutral-atom processor integrates atom motion with in-place entanglement to cut logical overhead, shown in Shor's variant, CX ladders, and [[16,4,4]] code experiments with 2-8x error improvements.
Two new heuristics reduce hardware-limited depth of commuting PPR groups by 10-20% on average (up to 50%) in QASMBench circuits compiled to PPRs.
GeneCS compiler reduces ancillary qubits and checks by over 85% on average for single- and cross-code logical operations on stabilizer codes while preserving error rates and scaling to over 10,000 qubits.
A Markov chain framework is introduced to model and optimize quantum memory dimensioning for preserving distilled EPR pairs in quantum networks.
The paper identifies four key hurdles in the transition from NISQ to FASQ quantum computers and argues that targeting them will accelerate progress toward useful quantum advantage.
citing papers explorer
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The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes
Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
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Parallel Logical Measurements via Quantum Code Surgery
A new code surgery protocol measures t logically disjoint Pauli products on any LDPC code using O(t ω (log t + log³ω)) ancillas in O(d) time while preserving LDPC property and fault distance.
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INJEQT: Improved Magic-State Injection Protocol for Fault-Tolerant Quantum Extractor Architectures
INJEQT reduces synthillation error by up to 22x, wall-clock time by 13x, and space-time cost by 7.2x in extractor FTQC architectures via auxiliary Rz synthesis and pre-fetching.
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CAbLECAR: efficiently scheduling QLDPC codes on a tileable spin qubit chip with shuttling
CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical error rates over surface codes.
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Assessing System Capabilities and Bottlenecks of an Early Fault-Tolerant Bicycle Architecture
Syn@fac optimization reduces estimated circuit failure probability by a factor of 9 on average across non-Clifford benchmarks for bivariate bicycle code modular FTQC architectures, with additional gains from transvection deferral and Clifford insertion.
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Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
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Towards Ultra-High-Rate Quantum Error Correction with Reconfigurable Atom Arrays
A family of quantum LDPC codes with encoding rates exceeding 1/2 achieves logical error rates of 10^{-13} per round on atom arrays under 0.1% circuit noise using hierarchical decoding.
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Shor's algorithm is possible with as few as 10,000 reconfigurable atomic qubits
Shor's algorithm for cryptographically relevant problems becomes feasible on neutral-atom systems with as few as 10,000 reconfigurable physical qubits via high-rate quantum error correction.
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Accelerating Fault-Tolerant Quantum Computation with Good qLDPC Codes
A new scheme for fault-tolerant quantum computation on qLDPC codes achieves constant qubit overhead and time overhead O(d^{1+o(1)}) for good codes, faster than prior code surgery methods for a<2.
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Demonstration of a Logical Architecture Uniting Motion and In-Place Entanglement
Neutral-atom processor integrates atom motion with in-place entanglement to cut logical overhead, shown in Shor's variant, CX ladders, and [[16,4,4]] code experiments with 2-8x error improvements.
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Optimizing Parallel Execution of Commuting Pauli Product Rotations
Two new heuristics reduce hardware-limited depth of commuting PPR groups by 10-20% on average (up to 50%) in QASMBench circuits compiled to PPRs.
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GeneCS: Synthesizing Resource-Efficient Code Surgery for Arbitrary Quantum Stabilizer Codes
GeneCS compiler reduces ancillary qubits and checks by over 85% on average for single- and cross-code logical operations on stabilizer codes while preserving error rates and scaling to over 10,000 qubits.
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Dimensioning of Quantum Memories for Distilled Quantum EPR Packets
A Markov chain framework is introduced to model and optimize quantum memory dimensioning for preserving distilled EPR pairs in quantum networks.
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Mind the gaps: The fraught road to quantum advantage
The paper identifies four key hurdles in the transition from NISQ to FASQ quantum computers and argues that targeting them will accelerate progress toward useful quantum advantage.