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arxiv: 2604.19481 · v1 · submitted 2026-04-21 · 🪐 quant-ph · cs.ET

Recognition: unknown

Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture

Felix Tripier , Woo Chang Chung , Jacob Young , Safwan Alam , Bryce Bjork , Aharon Brodutch , Finn Lasse Buessen , Nolan J. Coble
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Thomas Dellaert Dmitri Maslov Martin Roetteler Edwin Tham Mark Webster Min Ye John Gamble Andrii Maksymov J. P. Marceaux Nicolas Delfosse
Authors on Pith no claims yet

Pith reviewed 2026-05-10 02:12 UTC · model grok-4.3

classification 🪐 quant-ph cs.ET
keywords fault-tolerant quantum computingtrapped ionsLDPC codescat statesquantum error correctionlogical qubitsquantum simulation
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The pith

A walking cat architecture based on LDPC codes and cat states enables fault-tolerant trapped-ion quantum computing with hundreds of logical qubits using thousands of physical qubits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper proposes the walking cat architecture for trapped-ion devices, relying on a cat factory to produce cat states that are distributed and consumed for logical operations under low-density parity-check error correction. This blueprint includes a compiler, error-correction protocols, micro-architecture, and decoder, all grounded in experimentally demonstrated components. A dense implementation encodes 22 logical qubits per block and scales to 110 logical qubits performing one million T gates daily with 2,514 physical qubits. Such a system could simulate a 100-site Heisenberg model to chemical accuracy in one month with 10,000 physical qubits, entering the realm of classically intractable problems. Readers should care because it outlines a practical path to useful quantum computation without waiting for unproven hardware advances.

Core claim

The walking cat architecture uses a cat factory to generate cat states distributed across the machine for performing logical operations, combined with LDPC codes for fault tolerance, providing a complete blueprint that achieves high logical qubit counts and gate rates with modest physical resources while emphasizing simplicity for near-term implementation.

What carries the argument

The cat factory, which produces cat states distributed throughout the machine and consumed to perform logical operations within an LDPC code framework.

Load-bearing premise

The design assumes that cat-state production, LDPC decoding, and connectivity can be scaled to the required speed and fidelity in a large trapped-ion system using only currently demonstrated small-device components.

What would settle it

A measurement showing that the required cat-state fidelity or decoder throughput cannot be maintained when operating multiple memory blocks simultaneously would disprove the feasibility of the proposed performance levels.

Figures

Figures reproduced from arXiv: 2604.19481 by Aharon Brodutch, Andrii Maksymov, Bryce Bjork, Dmitri Maslov, Edwin Tham, Felix Tripier, Finn Lasse Buessen, Jacob Young, John Gamble, J. P. Marceaux, Mark Webster, Martin Roetteler, Min Ye, Nicolas Delfosse, Nolan J. Coble, Safwan Alam, Thomas Dellaert, Woo Chang Chung.

Figure 1
Figure 1. Figure 1: FIG. 1: Layers of abstractions of an FTQC architecture. [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2: Simplified representation of a walking cat [PITH_FULL_IMAGE:figures/full_fig_p012_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3: Representation of the main components in the [PITH_FULL_IMAGE:figures/full_fig_p013_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4: A memory block consists of four rows: a row of [PITH_FULL_IMAGE:figures/full_fig_p013_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5: The magic factory is built on top of a memory [PITH_FULL_IMAGE:figures/full_fig_p014_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6: Like the memory block and magic factory, the [PITH_FULL_IMAGE:figures/full_fig_p015_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7: Decomposition of the logical operations from the logical instruction set. [PITH_FULL_IMAGE:figures/full_fig_p020_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8: Orange square boxes represent Pauli [PITH_FULL_IMAGE:figures/full_fig_p021_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9: We use the notation of Fig. 8. (a) [PITH_FULL_IMAGE:figures/full_fig_p022_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11: Tradeoff between the number of logical qubits [PITH_FULL_IMAGE:figures/full_fig_p025_11.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10: Qubit allocations in instances of walking cat [PITH_FULL_IMAGE:figures/full_fig_p025_10.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12: Examples of different ring shifts for [PITH_FULL_IMAGE:figures/full_fig_p027_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13: Example of a syndrome extraction circuit for a BB4 code with [PITH_FULL_IMAGE:figures/full_fig_p029_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14: Teleportation-based data-qubit leakage [PITH_FULL_IMAGE:figures/full_fig_p033_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15: Logical error rate as a function of the loss rate [PITH_FULL_IMAGE:figures/full_fig_p033_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16: Logical error rate as a function of the leakage [PITH_FULL_IMAGE:figures/full_fig_p034_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: FIG. 18: Sensitivity analysis showing the impact of [PITH_FULL_IMAGE:figures/full_fig_p035_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: FIG. 19: Logical error rate per SEC versus beacon [PITH_FULL_IMAGE:figures/full_fig_p035_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: FIG. 20: Logical error rate per SEC versus beacon [PITH_FULL_IMAGE:figures/full_fig_p036_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: FIG. 21: Visual depiction of the cat state preparation [PITH_FULL_IMAGE:figures/full_fig_p038_21.png] view at source ↗
Figure 23
Figure 23. Figure 23: FIG. 23: Simulation results (using [PITH_FULL_IMAGE:figures/full_fig_p041_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: FIG. 24: Qubit loss probability for a 30 qubit cat state. [PITH_FULL_IMAGE:figures/full_fig_p041_24.png] view at source ↗
Figure 22
Figure 22. Figure 22: FIG. 22: Errors and rejection during verification for a [PITH_FULL_IMAGE:figures/full_fig_p041_22.png] view at source ↗
Figure 25
Figure 25. Figure 25: FIG. 25: Using a cat state to measure [PITH_FULL_IMAGE:figures/full_fig_p043_25.png] view at source ↗
Figure 27
Figure 27. Figure 27: FIG. 27: An error-corrected logical measurement [PITH_FULL_IMAGE:figures/full_fig_p044_27.png] view at source ↗
Figure 26
Figure 26. Figure 26: FIG. 26: An error-detected logical measurement ( [PITH_FULL_IMAGE:figures/full_fig_p044_26.png] view at source ↗
Figure 28
Figure 28. Figure 28: FIG. 28: ( [PITH_FULL_IMAGE:figures/full_fig_p045_28.png] view at source ↗
Figure 29
Figure 29. Figure 29: FIG. 29: Block diagram of simulation circuits. [PITH_FULL_IMAGE:figures/full_fig_p045_29.png] view at source ↗
Figure 31
Figure 31. Figure 31: shows the logical performance of ECM-5, 7, and 9, applied to the memory code Q102. Shaded regions depict 95% confidence bands, derived from fitting and extrapolating simulation datapoints for each r with the ansatz: p fit ECM(r, p) = p ⌈r/2⌉ expα+βp+γp2 , with fit param￾eters α, β, γ. Dashed lines show the heuristic of Eq. (17). From these simulations, we determine C2 = 3.4 ± 0.4. Close agreement between … view at source ↗
Figure 30
Figure 30. Figure 30: shows bit-flip error rates for a single cat￾based measurement (equivalently, ECM-1), across a range of physical noise rates and Pauli weights, target￾ing a Q102 memory code block. Fitting the heuristic of Eq. (15) to this numerical data yields C1 = 2.1±0.01. A similar numerical experiment on a Q70 distillation code block yields identical results for C1. 2. ECM for the Q102 code 10 4 10 3 Physical Noise Ra… view at source ↗
Figure 32
Figure 32. Figure 32: FIG. 32: Logical bit error rate for [PITH_FULL_IMAGE:figures/full_fig_p047_32.png] view at source ↗
Figure 35
Figure 35. Figure 35: shows a logical measurement across two code blocks, comprised of a Q70 and a Q102 code. Such a logical measurement is used, for instance, to implement a logical instruction (LM2), to perform a logical T gate in the Q102 code by consuming a magic state stored in the Q70 code, or to perform inter-block logical CX gates. In [PITH_FULL_IMAGE:figures/full_fig_p047_35.png] view at source ↗
Figure 36
Figure 36. Figure 36: FIG. 36: Duration of adaptive logical measurements [PITH_FULL_IMAGE:figures/full_fig_p048_36.png] view at source ↗
Figure 37
Figure 37. Figure 37: FIG. 37: Distribution of weights of all [PITH_FULL_IMAGE:figures/full_fig_p050_37.png] view at source ↗
Figure 40
Figure 40. Figure 40: FIG. 40: Distribution of weights of all [PITH_FULL_IMAGE:figures/full_fig_p050_40.png] view at source ↗
Figure 41
Figure 41. Figure 41: FIG. 41: Distribution of stabilizer-optimized weights of [PITH_FULL_IMAGE:figures/full_fig_p051_41.png] view at source ↗
Figure 43
Figure 43. Figure 43: FIG. 43: IS+H-based implementations of logical [PITH_FULL_IMAGE:figures/full_fig_p052_43.png] view at source ↗
Figure 44
Figure 44. Figure 44: FIG. 44: Fault locations contributing to an injected [PITH_FULL_IMAGE:figures/full_fig_p054_44.png] view at source ↗
Figure 45
Figure 45. Figure 45: FIG. 45 [PITH_FULL_IMAGE:figures/full_fig_p055_45.png] view at source ↗
Figure 46
Figure 46. Figure 46: shows an IS+H-based implementation of a logical controlled-H¯ gate. The construction uses the standard identity CH = (I ⊗ Ry(π/4)) CZ (I ⊗ Ry(−π/4)), P0 L0 |H⟩ Y Y SEC EDM r Z RY(π 2) RY(π 2) X Z Y FIG. 45: H-state injection from a physical ancilla P0 onto a logical qubit L0, implemented in a code block with SEC-level scheduling. This realizes the IS+H-based circuit for logical Ry(π/4), with the hybrid jo… view at source ↗
Figure 47
Figure 47. Figure 47: Each logical Ry(±π/4) subcircuit uses a physical ancilla prepared in |H⟩ and an EDM for the hybrid Y Y¯ measurement. The Ry(π/4) code-block implementation can be seen in [PITH_FULL_IMAGE:figures/full_fig_p055_47.png] view at source ↗
Figure 47
Figure 47. Figure 47: FIG. 47: Implementation of the logical controlled- [PITH_FULL_IMAGE:figures/full_fig_p056_47.png] view at source ↗
Figure 48
Figure 48. Figure 48: This is considerably cheaper than realizing the [PITH_FULL_IMAGE:figures/full_fig_p056_48.png] view at source ↗
Figure 49
Figure 49. Figure 49: FIG. 49 [PITH_FULL_IMAGE:figures/full_fig_p057_49.png] view at source ↗
Figure 50
Figure 50. Figure 50: FIG. 50: Circuit for the [PITH_FULL_IMAGE:figures/full_fig_p060_50.png] view at source ↗
Figure 51
Figure 51. Figure 51: Justification. Each of the three terminal logical Pauli readouts in [PITH_FULL_IMAGE:figures/full_fig_p060_51.png] view at source ↗
Figure 51
Figure 51. Figure 51: FIG. 51 [PITH_FULL_IMAGE:figures/full_fig_p061_51.png] view at source ↗
Figure 52
Figure 52. Figure 52: FIG. 52 [PITH_FULL_IMAGE:figures/full_fig_p064_52.png] view at source ↗
Figure 53
Figure 53. Figure 53: FIG. 53: For each of the subsystem allocations from [PITH_FULL_IMAGE:figures/full_fig_p065_53.png] view at source ↗
Figure 54
Figure 54. Figure 54: FIG. 54 [PITH_FULL_IMAGE:figures/full_fig_p066_54.png] view at source ↗
Figure 56
Figure 56. Figure 56: FIG. 56: Probability distribution histograms for [PITH_FULL_IMAGE:figures/full_fig_p072_56.png] view at source ↗
Figure 57
Figure 57. Figure 57: FIG. 57: Logical instruction (DMX) enriched by [PITH_FULL_IMAGE:figures/full_fig_p073_57.png] view at source ↗
Figure 58
Figure 58. Figure 58: FIG. 58: Simplified illustration of potential well [PITH_FULL_IMAGE:figures/full_fig_p077_58.png] view at source ↗
Figure 60
Figure 60. Figure 60: FIG. 60: Mapping of the three-ring framework to a [PITH_FULL_IMAGE:figures/full_fig_p081_60.png] view at source ↗
Figure 62
Figure 62. Figure 62 [PITH_FULL_IMAGE:figures/full_fig_p082_62.png] view at source ↗
Figure 62
Figure 62. Figure 62: FIG. 62: Embedding of the [PITH_FULL_IMAGE:figures/full_fig_p083_62.png] view at source ↗
Figure 63
Figure 63. Figure 63: FIG. 63: Embedding of the CH2 magic factory. Dark purple (yellow) circles represent data (beacon) qubits. Light [PITH_FULL_IMAGE:figures/full_fig_p084_63.png] view at source ↗
Figure 64
Figure 64. Figure 64: FIG. 64: Operations of weight-18 cat factory in a four-row layout. Dark (light) orange circles represent cat data [PITH_FULL_IMAGE:figures/full_fig_p085_64.png] view at source ↗
Figure 65
Figure 65. Figure 65: FIG. 65: Cat-based measurement interface between a [PITH_FULL_IMAGE:figures/full_fig_p087_65.png] view at source ↗
Figure 66
Figure 66. Figure 66: FIG. 66: Heisenberg interaction term [PITH_FULL_IMAGE:figures/full_fig_p088_66.png] view at source ↗
Figure 69
Figure 69. Figure 69: FIG. 69: Single-shot execution time estimates of the [PITH_FULL_IMAGE:figures/full_fig_p089_69.png] view at source ↗
Figure 68
Figure 68. Figure 68: FIG. 68: Single-shot execution time estimates of the [PITH_FULL_IMAGE:figures/full_fig_p089_68.png] view at source ↗
Figure 70
Figure 70. Figure 70: FIG. 70: Single-shot execution time estimates of the [PITH_FULL_IMAGE:figures/full_fig_p090_70.png] view at source ↗
Figure 71
Figure 71. Figure 71: FIG. 71: Iterative QPE on the prepared state [PITH_FULL_IMAGE:figures/full_fig_p090_71.png] view at source ↗
Figure 72
Figure 72. Figure 72: FIG. 72: Ancilla-aided decomposition used for the [PITH_FULL_IMAGE:figures/full_fig_p091_72.png] view at source ↗
Figure 73
Figure 73. Figure 73: FIG. 73 [PITH_FULL_IMAGE:figures/full_fig_p100_73.png] view at source ↗
Figure 74
Figure 74. Figure 74: FIG. 74: Probability distribution histograms for [PITH_FULL_IMAGE:figures/full_fig_p103_74.png] view at source ↗
Figure 75
Figure 75. Figure 75: FIG. 75: A [PITH_FULL_IMAGE:figures/full_fig_p108_75.png] view at source ↗
Figure 76
Figure 76. Figure 76: FIG. 76: A [PITH_FULL_IMAGE:figures/full_fig_p108_76.png] view at source ↗
read the original abstract

We propose a fault-tolerant quantum computer architecture for trapped-ion devices, which we call the walking cat architecture. Our blueprint includes a compiler, a detailed description of all the quantum error-correction protocols, a micro-architecture, a sufficiently fast decoder, and thorough simulations. The backbone of the architecture is a cat factory, producing cat states distributed throughout the machine, which are consumed to perform logical operations. The walking cat architecture is based entirely on a modern quantum error-correction approach called low-density parity-check (LDPC) codes. We identify promising instances of the walking cat architecture, such as (1) a simple architecture based on a single LDPC code, (2) a fast architecture based on fast logical gates relying on a [[70, 6, 9]] code, equipped with Clifford-frame tracking for any 6-qubit Clifford gate, and (3) a dense architecture based on a [[102, 22, 9]]] code encoding 22 logical qubits per memory block. Our dense architecture provides a design with 110 logical qubits executing about one million T gates per day using only 2,514 physical qubits. We estimate that the quantum Hamiltonian simulation of a Heisenberg model on 100 sites can be executed within one month with 10,000 physical qubits, including all shots required to achieve chemical accuracy, suggesting that such a device could enter the regime of classically intractable physics simulations. Our design relies on hardware components that have been experimentally demonstrated on small devices. We emphasize simplicity over hypothetical performance to facilitate the practical realization of this machine. Based on this approach, we believe that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates can be built in the near term, providing a platform to explore a broad range of applications.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript proposes the walking cat architecture for fault-tolerant quantum computing with trapped ions, based on low-density parity-check (LDPC) codes and a cat factory that produces cat states for logical operations. It includes a compiler, detailed quantum error-correction protocols, micro-architecture, a fast decoder, and simulations. Specific designs are presented, including a dense architecture using a [[102, 22, 9]] code that supports 110 logical qubits executing about one million T gates per day with 2,514 physical qubits, plus an estimate that a Heisenberg model simulation on 100 sites can be performed in one month with 10,000 physical qubits (including shots for chemical accuracy). The design emphasizes use of only experimentally demonstrated hardware components on small devices.

Significance. If the scaling assumptions hold, the work provides a concrete, hardware-grounded blueprint for near-term fault-tolerant quantum computers with hundreds of logical qubits using trapped ions and LDPC codes. Strengths include the inclusion of a compiler, protocols, decoder design, and simulations, plus the focus on simplicity to facilitate practical realization. This could enable exploration of applications such as quantum Hamiltonian simulations beyond classical reach.

major comments (3)
  1. [Abstract] Abstract: The performance claim of approximately one million T gates per day for the dense architecture (110 logical qubits on 2,514 physical qubits) is presented as an output of simulations, but it reduces to assumed inputs for cat-state production rates, gate durations, error rates, and decoder latency without an accompanying end-to-end timing or error-budget model.
  2. [Dense architecture section] Section on dense architecture and cat factory: The architecture's throughput relies on the cat factory delivering high-fidelity cat states at a rate matching the logical clock and the LDPC decoder completing within the error-correction cycle. While the paper states that all primitives have been demonstrated on small devices, the quantitative mapping to aggregate rates, connectivity, and fidelity across thousands of ions (including ion-chain motional modes and crosstalk) lacks a comprehensive model, which is load-bearing for the 1M T-gate/day figure.
  3. [Performance estimates section] Section on Heisenberg simulation estimate: The claim that the 100-site Heisenberg model simulation can be executed within one month with 10,000 physical qubits (including all shots for chemical accuracy) appears to depend on gate durations, error rates, and decoding latency fitted from prior small-scale experiments rather than derived from a full system model, introducing potential circularity in the performance projections.
minor comments (2)
  1. [Introduction or code description section] The LDPC code parameters ([[70,6,9]] and [[102,22,9]]) should be explicitly defined (length, dimension, distance) on first use in the main text to improve clarity for readers unfamiliar with the notation.
  2. [Micro-architecture section] Any architecture diagrams or timing figures would benefit from explicit labels for physical-to-logical qubit mappings and operation latencies to aid verification of the micro-architecture claims.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the careful reading and constructive comments on our performance claims. We have revised the manuscript to strengthen the modeling and justification for the throughput estimates while preserving the focus on experimentally demonstrated components.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The performance claim of approximately one million T gates per day for the dense architecture (110 logical qubits on 2,514 physical qubits) is presented as an output of simulations, but it reduces to assumed inputs for cat-state production rates, gate durations, error rates, and decoder latency without an accompanying end-to-end timing or error-budget model.

    Authors: We agree that the abstract figure benefits from explicit supporting analysis. In the revised manuscript we have added a new subsection (Section 5.3) that presents an end-to-end timing and error-budget model. The model decomposes the logical clock cycle into cat-state production, logical gate execution, syndrome extraction, and decoding latency, with each term derived from the measured rates and fidelities reported in the cited small-device experiments. Conservative margins for overhead are included, and the resulting throughput is shown to be consistent with the one-million-T-gate-per-day claim under the stated assumptions. revision: yes

  2. Referee: [Dense architecture section] Section on dense architecture and cat factory: The architecture's throughput relies on the cat factory delivering high-fidelity cat states at a rate matching the logical clock and the LDPC decoder completing within the error-correction cycle. While the paper states that all primitives have been demonstrated on small devices, the quantitative mapping to aggregate rates, connectivity, and fidelity across thousands of ions (including ion-chain motional modes and crosstalk) lacks a comprehensive model, which is load-bearing for the 1M T-gate/day figure.

    Authors: We acknowledge that a fully microscopic simulation of motional-mode coupling and crosstalk for 2514 ions is beyond the scope of the present work. In the revision we have expanded the micro-architecture description (Section 4.2) with a quantitative estimate of crosstalk suppression using the demonstrated sympathetic cooling and segmented trap techniques from the cited experiments. We also provide a conservative bound on residual motional heating rates and show that the parallel cat-factory layout keeps the aggregate error contribution below the LDPC threshold. These additions make the scaling assumptions more transparent without claiming a complete many-body model. revision: partial

  3. Referee: [Performance estimates section] Section on Heisenberg simulation estimate: The claim that the 100-site Heisenberg model simulation can be executed within one month with 10,000 physical qubits (including all shots for chemical accuracy) appears to depend on gate durations, error rates, and decoding latency fitted from prior small-scale experiments rather than derived from a full system model, introducing potential circularity in the performance projections.

    Authors: The input parameters are taken directly from independent small-scale trapped-ion experiments (references [X,Y,Z] in the manuscript) and are not fitted to the large-scale projection. To eliminate any appearance of circularity we have added Table 2, which lists every numerical assumption together with its experimental source and the conservative margin applied. The one-month estimate is obtained by propagating these fixed values through the resource-counting compiler and the LDPC decoder latency model; no parameters were adjusted to match the target runtime. revision: yes

Circularity Check

0 steps flagged

No significant circularity in the architecture proposal or estimates

full rationale

The paper presents a trapped-ion architecture blueprint relying on LDPC codes and cat-state factories, with performance figures (110 logical qubits, ~1M T gates/day on 2514 physical qubits, one-month Heisenberg simulation) explicitly described as design outputs and simulation estimates based on hardware parameters from small-scale experiments. These are not framed as independent first-principles predictions that reduce to the inputs by construction. No self-definitional steps, fitted parameters renamed as predictions, load-bearing self-citations, or ansatz smuggling appear in the derivation chain. The work is self-contained as an engineering proposal with stated assumptions, qualifying for the default non-circular finding.

Axiom & Free-Parameter Ledger

1 free parameters · 2 axioms · 2 invented entities

The central claims rest on domain assumptions about hardware scalability and LDPC performance in ion traps plus newly introduced architectural elements whose performance is projected from simulations rather than first-principles derivation.

free parameters (1)
  • LDPC code parameters ([[70,6,9]] and [[102,22,9]])
    Specific code instances chosen to achieve target logical qubit counts and gate speeds; values are selected rather than derived from first principles.
axioms (2)
  • domain assumption Trapped-ion hardware can produce, distribute, and consume cat states at the required rate and fidelity when scaled
    Invoked throughout the cat factory and walking mechanism description.
  • domain assumption LDPC decoding can be performed sufficiently fast for real-time error correction without dominating the gate time
    Required for the claim of a sufficiently fast decoder.
invented entities (2)
  • Walking cat architecture no independent evidence
    purpose: Framework that produces and walks cat states to enable logical operations with LDPC codes in trapped ions
    Newly proposed integrated design; no independent evidence outside the paper.
  • Cat factory no independent evidence
    purpose: Component that generates cat states distributed throughout the machine
    Core novel element of the architecture; no independent evidence outside the paper.

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Reference graph

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