Experimental breakeven demonstration of a qLDPC code encoding 4 logical qubits in 18 physical qubits on trapped ions, with up to 9x lower logical error rate than prior superconducting implementations.
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Trapped- ion two-qubit gates with>99.99% fidelity without ground-state cooling,
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quant-ph 18years
2026 18roles
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Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
A rubric-guided GRPO pipeline fine-tunes a 7B LLM to synthesize quantum circuits achieving 3.31x T-gate compression with <1% hardware-constraint violations, validated on IBM and IonQ processors.
A noise model for trapped-ion multi-qubit gates shows that dominant error channels remain compatible with scalable rotated-surface-code quantum error correction when realistic experimental parameters are used.
A benchmarking framework decomposes shuttling protocols into primitives whose heating contributions combine algebraically to predict total excitations in ion-trap quantum processors, shown on an 8-qubit linear-transport design.
Demonstrates DC-voltage-controlled radial transport of a single ion through transition zones in a prototype ion trap chip for 2D quantum spring array architecture, with measurements of stray fields and heating rates.
Experimental demonstration of a multiplexing trapped-ion QPU using sample-and-hold circuits achieves motional heating rates below 1 phonon/s and expected gate errors below 10^{-4} for sampling intervals under 50 ms.
FTPrimitiveBench is a new benchmark suite for testing surface-code logical primitives under Pauli-biased, measurement-biased, and spatially non-uniform noise models, revealing that noise structure interacts distinctly with each primitive and decoder.
An architecture-aware unitary-synthesis transpiler is claimed to cut CNOT counts by 6-36% and run 39-940x faster than Qiskit/TKET/Pennylane on IQM Garnet and IBM Marrakesh circuits with 3-11 qubits.
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
Singly-ionized yttrium (89Y+) is positioned as a trapped-ion qubit with nuclear-spin storage, metastable manifolds, and isolated transitions for initialization, readout, and gates.
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring at 190k-381k qubits.
High motional frequency ion trapping reduces decoherence effects and accelerates experimental duty cycles in quantum information science.
Experimental demonstration of quantum collision models for Markovian dynamics on quantum hardware with up to 7 system qubits and 40 time steps, using hardware-specific ancilla strategies for local and nonlocal dissipation.
A software protocol measures and corrects trigger-synchronous coherent errors in trapped-ion qubits and qudits by updating control frequency and phase, raising single-qubit gate fidelity to 99.93(1)% and 16-level qudit algorithm success from 10(7)% to 70(9)%.
Concatenates Laflamme and Iceberg codes with selective filtering for a partially fault-tolerant quantum computation scheme that simulations indicate performs reliably at realistic noise levels.
A compilation scheme called Parity Twine achieved a 50-qubit unitary QFT with process fidelity ≈1e-2 on IBM Heron r3, and up to 52 qubits with plurality voting, surpassing prior unitary QFT demonstrations.
HUBO formulations for logistics problems offer qubit savings over QUBO at the expense of higher circuit depth, validated classically and simulated quantumly for small cases.
citing papers explorer
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Breakeven demonstration of quantum low-density parity-check codes
Experimental breakeven demonstration of a qLDPC code encoding 4 logical qubits in 18 physical qubits on trapped ions, with up to 9x lower logical error rate than prior superconducting implementations.
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The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes
Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
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RubriQ: Rubric-Guided Group Relative Policy Optimization for Constraint-Aware Quantum Circuit Synthesis
A rubric-guided GRPO pipeline fine-tunes a 7B LLM to synthesize quantum circuits achieving 3.31x T-gate compression with <1% hardware-constraint violations, validated on IBM and IonQ processors.
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Trapped-Ion Multiqubit Gates are Compatible with Scalable Quantum Error Correction
A noise model for trapped-ion multi-qubit gates shows that dominant error channels remain compatible with scalable rotated-surface-code quantum error correction when realistic experimental parameters are used.
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A framework for the benchmarking of transport-induced excitations in shuttling-based ion-trap quantum processors
A benchmarking framework decomposes shuttling protocols into primitives whose heating contributions combine algebraically to predict total excitations in ion-trap quantum processors, shown on an 8-qubit linear-transport design.
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Demonstration of transport in an ion trap design for two-dimensional lattices
Demonstrates DC-voltage-controlled radial transport of a single ion through transition zones in a prototype ion trap chip for 2D quantum spring array architecture, with measurements of stray fields and heating rates.
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Demonstration of a Multiplexing Trapped Ion Quantum Processing Unit
Experimental demonstration of a multiplexing trapped-ion QPU using sample-and-hold circuits achieves motional heating rates below 1 phonon/s and expected gate errors below 10^{-4} for sampling intervals under 50 ms.
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FTPrimitiveBench: A Benchmark Suite For Logical Computation Under Hardware-Motivated and Biased Noise Models
FTPrimitiveBench is a new benchmark suite for testing surface-code logical primitives under Pauli-biased, measurement-biased, and spatially non-uniform noise models, revealing that noise structure interacts distinctly with each primitive and decoder.
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Architecture-aware Unitary Synthesis
An architecture-aware unitary-synthesis transpiler is claimed to cut CNOT counts by 6-36% and run 39-940x faster than Qiskit/TKET/Pennylane on IQM Garnet and IBM Marrakesh circuits with 3-11 qubits.
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Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
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Yttrium ion as a platform for quantum information processing
Singly-ionized yttrium (89Y+) is positioned as a trapped-ion qubit with nuclear-spin storage, metastable manifolds, and isolated transitions for initialization, readout, and gates.
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Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring at 190k-381k qubits.
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A High Motional Frequency Ion Trapping Regime for Quantum Information Science
High motional frequency ion trapping reduces decoherence effects and accelerates experimental duty cycles in quantum information science.
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Simulating the Dynamics of Markovian Quantum Processes by Quantum Collision Models on Quantum Computers
Experimental demonstration of quantum collision models for Markovian dynamics on quantum hardware with up to 7 system qubits and 40 time steps, using hardware-specific ancilla strategies for local and nonlocal dissipation.
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Software compensation of trigger-synchronous control-frame errors in qubits and qudits
A software protocol measures and corrects trigger-synchronous coherent errors in trapped-ion qubits and qudits by updating control frequency and phase, raising single-qubit gate fidelity to 99.93(1)% and 16-level qudit algorithm success from 10(7)% to 70(9)%.
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Fire and ice: Partially fault-tolerant quantum computing with selective state filtering
Concatenates Laflamme and Iceberg codes with selective filtering for a partially fault-tolerant quantum computation scheme that simulations indicate performs reliably at realistic noise levels.
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Demonstrating Record Fidelity for the Quantum Fourier Transform
A compilation scheme called Parity Twine achieved a 50-qubit unitary QFT with process fidelity ≈1e-2 on IBM Heron r3, and up to 52 qubits with plurality voting, surpassing prior unitary QFT demonstrations.
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Quantum optimization beyond QUBO for industrial logistics and scheduling
HUBO formulations for logistics problems offer qubit savings over QUBO at the expense of higher circuit depth, validated classically and simulated quantumly for small cases.