A new method for unitary synthesis on quantum hardware cuts CNOT gates by up to 36% and compiles up to 553 times faster than standard tools on square and heavy-hex lattices.
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Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
Demonstrates DC-voltage-controlled radial transport of a single ion through transition zones in a prototype ion trap chip for 2D quantum spring array architecture, with measurements of stray fields and heating rates.
Experimental demonstration of a multiplexing trapped-ion QPU using sample-and-hold circuits achieves motional heating rates below 1 phonon/s and expected gate errors below 10^{-4} for sampling intervals under 50 ms.
FTPrimitiveBench is a new benchmark suite for testing surface-code logical primitives under Pauli-biased, measurement-biased, and spatially non-uniform noise models, revealing that noise structure interacts distinctly with each primitive and decoder.
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
Singly-ionized yttrium (89Y+) is positioned as a trapped-ion qubit with nuclear-spin storage, metastable manifolds, and isolated transitions for initialization, readout, and gates.
Parity Architecture delivers record ~0.01 fidelity for 50-qubit QFT on IBM hardware with super-exponential scaling improvement.
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring at 190k-381k qubits.
High motional frequency ion trapping reduces decoherence effects and accelerates experimental duty cycles in quantum information science.
Concatenates Laflamme and Iceberg codes with selective filtering for a partially fault-tolerant quantum computation scheme that simulations indicate performs reliably at realistic noise levels.
citing papers explorer
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Architecture-aware Unitary Synthesis
A new method for unitary synthesis on quantum hardware cuts CNOT gates by up to 36% and compiles up to 553 times faster than standard tools on square and heavy-hex lattices.
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The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes
Pinnacle Architecture using QLDPC codes reduces physical qubits needed to factor RSA-2048 to under 100,000 at 10^{-3} error rate.
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Demonstration of transport in an ion trap design for two-dimensional lattices
Demonstrates DC-voltage-controlled radial transport of a single ion through transition zones in a prototype ion trap chip for 2D quantum spring array architecture, with measurements of stray fields and heating rates.
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Demonstration of a Multiplexing Trapped Ion Quantum Processing Unit
Experimental demonstration of a multiplexing trapped-ion QPU using sample-and-hold circuits achieves motional heating rates below 1 phonon/s and expected gate errors below 10^{-4} for sampling intervals under 50 ms.
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FTPrimitiveBench: A Benchmark Suite For Logical Computation Under Hardware-Motivated and Biased Noise Models
FTPrimitiveBench is a new benchmark suite for testing surface-code logical primitives under Pauli-biased, measurement-biased, and spatially non-uniform noise models, revealing that noise structure interacts distinctly with each primitive and decoder.
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Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
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Yttrium ion as a platform for quantum information processing
Singly-ionized yttrium (89Y+) is positioned as a trapped-ion qubit with nuclear-spin storage, metastable manifolds, and isolated transitions for initialization, readout, and gates.
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Demonstrating Record Fidelity for the Quantum Fourier Transform
Parity Architecture delivers record ~0.01 fidelity for 50-qubit QFT on IBM hardware with super-exponential scaling improvement.
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Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring at 190k-381k qubits.
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A High Motional Frequency Ion Trapping Regime for Quantum Information Science
High motional frequency ion trapping reduces decoherence effects and accelerates experimental duty cycles in quantum information science.
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Fire and ice: Partially fault-tolerant quantum computing with selective state filtering
Concatenates Laflamme and Iceberg codes with selective filtering for a partially fault-tolerant quantum computation scheme that simulations indicate performs reliably at realistic noise levels.