Coset-based generalization of 2BGA codes produces new quantum LDPC codes with parameters such as [[48,8,6]] and competitive noise thresholds under BP-OSD decoding.
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Experimental breakeven demonstration of a qLDPC code encoding 4 logical qubits in 18 physical qubits on trapped ions, with up to 9x lower logical error rate than prior superconducting implementations.
A symmetry-co-designed high-rate QEC architecture with parallel STAR injection on bivariate bicycle codes achieves ~5.5x space savings for TFIM and Fermi-Hubbard simulations versus surface-code STAR.
Full extractors for HGP codes are built to enable logical processing via PBC without compilation overhead, with sizes 50-80% of base codes and low error rates in simulations.
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
GeneCS compiler reduces ancillary qubits and checks by over 85% on average for single- and cross-code logical operations on stabilizer codes while preserving error rates and scaling to over 10,000 qubits.
Biased-noise ancillas (phase flips only) in bicycle bivariate and cyclic hypergraph product QLDPC codes increase effective fault distance, reduce short loops, and improve logical error rate by nearly 10x at 2e-3 circuit noise when bit flips are 50x rarer.
citing papers explorer
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Breaking the bicycle frame: Coset-based quantum LDPC codes
Coset-based generalization of 2BGA codes produces new quantum LDPC codes with parameters such as [[48,8,6]] and competitive noise thresholds under BP-OSD decoding.
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Breakeven demonstration of quantum low-density parity-check codes
Experimental breakeven demonstration of a qLDPC code encoding 4 logical qubits in 18 physical qubits on trapped ions, with up to 9x lower logical error rate than prior superconducting implementations.
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Fast and Parallel High-Rate STAR Architecture for Megaquop Quantum Simulation
A symmetry-co-designed high-rate QEC architecture with parallel STAR injection on bivariate bicycle codes achieves ~5.5x space savings for TFIM and Fermi-Hubbard simulations versus surface-code STAR.
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Full Extractors for Logical Processing in Hypergraph Product Codes
Full extractors for HGP codes are built to enable logical processing via PBC without compilation overhead, with sizes 50-80% of base codes and low error rates in simulations.
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Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture
A trapped-ion architecture based on LDPC codes and cat-state factories achieves 110 logical qubits and one million T gates per day using 2514 physical qubits, with estimates for Heisenberg model simulation on 100 sites in one month using 10000 qubits.
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GeneCS: Synthesizing Resource-Efficient Code Surgery for Arbitrary Quantum Stabilizer Codes
GeneCS compiler reduces ancillary qubits and checks by over 85% on average for single- and cross-code logical operations on stabilizer codes while preserving error rates and scaling to over 10,000 qubits.
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Untangling QLDPC Codes with Biased Noise Ancilla
Biased-noise ancillas (phase flips only) in bicycle bivariate and cyclic hypergraph product QLDPC codes increase effective fault distance, reduce short loops, and improve logical error rate by nearly 10x at 2e-3 circuit noise when bit flips are 50x rarer.