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arxiv: 2604.18714 · v1 · submitted 2026-04-20 · 🪐 quant-ph

Recognition: unknown

Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures

Kun Liu , Takahiro Tsunoda , Sophia H. Xue , Evan McKinney , Zeyuan Zhou , Shifan Xu , Robert J. Schoelkopf , Yongshan Ding
Authors on Pith no claims yet

Pith reviewed 2026-05-10 04:42 UTC · model grok-4.3

classification 🪐 quant-ph
keywords quantum LDPC codesbivariate bicycle codestoric oscillator networkquantum routingsuperconducting qubitsfault-tolerant computingerror correction
0
0 comments X

The pith

A 2D toric network of oscillators routes bivariate bicycle quantum LDPC codes using only O(sqrt(n)) long-range couplers.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper presents a hardware-software co-design for implementing bivariate bicycle quantum LDPC codes on superconducting circuits with limited connectivity. It introduces a programmable 2D toric network of oscillators as a communication fabric that handles the required long-range stabilizer measurements. This reduces the number of long-range couplers from O(n) to O(sqrt(n)). The design uses dual-rail qubits and gates like Swap-Wait-Swap and beamsplitter SWAPs to achieve high-fidelity operations with low latency and maximum parallelism via code symmetries. Circuit-level simulations with realistic noise show a logical error rate of 3.06% per logical qubit per cycle for the [[18,4,4]] code, which is 2.6 times lower than previous results.

Core claim

The paper establishes that a 2D toric network of oscillators can serve as an efficient communication fabric for routing the long-range interactions in bivariate bicycle codes. By exploiting code symmetries for parallel gate execution and employing dual-rail encoding with specific swap gates, the architecture achieves scalable syndrome extraction cycles while requiring only square-root scaling in long-range couplers. Simulations confirm improved logical error rates under realistic hardware noise.

What carries the argument

The 2D toric network of oscillators acting as a flexible communication fabric between qubit sites, supporting Swap-Wait-Swap gates and beamsplitter SWAPs for long-range two-qubit operations.

Load-bearing premise

The 2D toric network of oscillators can be implemented with high-fidelity, low-latency long-range gates matching the realistic noise model, without unaccounted hardware imperfections or connectivity limits.

What would settle it

Implementing a prototype 2D toric oscillator network on superconducting hardware and comparing the measured logical error rate for the [[18,4,4]] BB code against the simulated 3.06% value.

Figures

Figures reproduced from arXiv: 2604.18714 by Evan McKinney, Kun Liu, Robert J. Schoelkopf, Shifan Xu, Sophia H. Xue, Takahiro Tsunoda, Yongshan Ding, Zeyuan Zhou.

Figure 1
Figure 1. Figure 1: FIG. 1. (a) Programmable communication network. Com [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. (a) Fixed-coupler layout. Each check qubit interacts with four nearest neighbors plus two long-range partners under [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. (a) Dual-rail+SWS implementation of a long-range CZ on a 2D toric oscillator network. (b) Compilation into [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Search layout. (a,b) Stack the four types of tori on [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 4
Figure 4. Figure 4: (c), shifting the X torus right by 2 and up by 1 leaves all interaction directions unchanged. Formally, if the solid edge corresponds to A1α = β, then the dotted edge corresponds to A1(αX2) = βX2 = βL2, showing that torus translations preserve interaction directions. To minimize the maximum gate distance we follow the procedure in [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. XY routing on torus. We first route the mode along the X axis (horizontal direction). The red pins (X checks) indicate [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Define [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. (a) The number of routed 2Q gates in each round of [PITH_FULL_IMAGE:figures/full_fig_p008_10.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Comparison of the long-range couplers for the fixed [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. Comparison of the 2Q gate implementations. [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. 2Q gate error rate breakdown of dual-rail+SWS [PITH_FULL_IMAGE:figures/full_fig_p009_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. Contour plot of the worst-case [PITH_FULL_IMAGE:figures/full_fig_p009_13.png] view at source ↗
read the original abstract

Quantum low-density parity-check codes are promising candidates towards scalable fault-tolerant quantum computation. Among these, bivariate bicycle (BB) codes offer superior encoding rates and large code distance compared to surface codes. However, their requirement on long-range stabilizer measurements poses significant challenges for implementation on realistic hardware with limited connectivity, such as superconducting circuit platforms. In this work, we introduce a novel hardware-software co-design that leverages a programmable communication network architecture to address these limitations. Our approach utilizes a 2D toric network of oscillators as a flexible communication fabric linking qubits at each site. Such architecture significantly reduces the number of long-range couplers required from $O(n)$ to $O(\sqrt{n})$. Dual-rail qubits, along with native gates including Swap-Wait-Swap gates and beamsplitter SWAPs, ensure that long-range two-qubit gates can be executed with high fidelity and low latency. To further enhance performance, our qubit layout and routing algorithm utilize symmetries of the codes and enable maximum parallelism for long-range two-qubit gates, maintaining a low syndrome extraction cycle duration and scalability over the code length. We perform circuit-level simulation with realistic noise modeling based on experimental hardware parameters, observing an logical error rate per logical qubit per cycle of 3.06\% for $[[18, 4, 4]]$ BB code, 2.6$\times$ less than the existing experimental result. These findings provide a practical roadmap and identify key technological advancements needed to achieve low-overhead fault-tolerant quantum computing at scale.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript proposes a hardware-software co-design for implementing bivariate bicycle (BB) quantum LDPC codes on superconducting platforms with limited connectivity. It introduces a programmable 2D toric network of oscillators as a flexible communication fabric that reduces long-range couplers from O(n) to O(sqrt(n)), uses dual-rail qubits with native Swap-Wait-Swap and beamsplitter SWAP gates for high-fidelity long-range operations, and employs a symmetry-aware routing algorithm to maximize parallelism while keeping syndrome extraction cycles short. Circuit-level simulations with realistic noise modeling based on experimental parameters report a logical error rate per logical qubit per cycle of 3.06% for the [[18,4,4]] BB code, stated to be 2.6× lower than existing experimental results.

Significance. If the central hardware assumptions hold, the work provides a concrete and scalable route to realizing high-rate LDPC codes on near-term hardware, substantially lowering connectivity overhead compared with direct long-range coupling schemes. The emphasis on code symmetries for parallel routing and the reported error-rate improvement constitute a practical contribution toward low-overhead fault-tolerant quantum computation.

major comments (2)
  1. [Abstract] Abstract and simulation results: the reported 3.06% logical error rate per logical qubit per cycle (and the 2.6× improvement) is obtained from circuit-level simulations whose exact noise parameters, gate error rates, circuit decompositions of the Swap-Wait-Swap and beamsplitter SWAP operations, and comparison baselines are not specified. This prevents independent verification of whether the performance numbers are robust or sensitive to post-hoc choices in the noise model.
  2. [Hardware Architecture] Hardware architecture and assumptions: the central claims rest on the 2D toric oscillator network supporting long-range gates at fidelities and latencies that exactly match the modeled realistic noise without additional imperfections (crosstalk, calibration drift, or path-dependent latency). No sensitivity analysis or bounds are given on how deviations from this assumption would propagate to the logical error rate, leaving the 3.06% figure and the O(sqrt(n)) coupler reduction vulnerable to unmodeled hardware effects.
minor comments (1)
  1. [Abstract] The abstract contains the grammatical error 'an logical error rate'; this should be corrected to 'a logical error rate'.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their thorough review and valuable feedback on our manuscript. We address each major comment below with specific clarifications and commit to revisions that enhance transparency and robustness without altering the core contributions.

read point-by-point responses

  1. Referee: [Abstract] Abstract and simulation results: the reported 3.06% logical error rate per logical qubit per cycle (and the 2.6× improvement) is obtained from circuit-level simulations whose exact noise parameters, gate error rates, circuit decompositions of the Swap-Wait-Swap and beamsplitter SWAP operations, and comparison baselines are not specified. This prevents independent verification of whether the performance numbers are robust or sensitive to post-hoc choices in the noise model.

    Authors: We agree that additional detail on the simulation setup is necessary for independent verification. The noise model in the manuscript is constructed from experimental parameters in the superconducting qubit literature (e.g., T1/T2 times, gate durations, and error rates from recent device characterizations), but we acknowledge that the abstract and main text do not list every numerical value or decomposition explicitly. In the revised version we will add a new subsection (and an accompanying table) that specifies: (i) all single- and two-qubit gate error rates and durations used, (ii) the exact gate decompositions and pulse sequences for Swap-Wait-Swap and beamsplitter SWAP operations, (iii) the precise circuit-level noise model (including measurement and reset errors), and (iv) the exact baseline circuits and codes against which the 2.6× improvement is measured. These additions will allow readers to reproduce the 3.06 % figure and test its sensitivity to parameter choices. revision: yes

  2. Referee: [Hardware Architecture] Hardware architecture and assumptions: the central claims rest on the 2D toric oscillator network supporting long-range gates at fidelities and latencies that exactly match the modeled realistic noise without additional imperfections (crosstalk, calibration drift, or path-dependent latency). No sensitivity analysis or bounds are given on how deviations from this assumption would propagate to the logical error rate, leaving the 3.06% figure and the O(sqrt(n)) coupler reduction vulnerable to unmodeled hardware effects.

    Authors: The referee correctly notes the absence of a sensitivity study. Our noise model assumes that the programmable toric network can realize the modeled long-range operations at the stated fidelities and latencies; we did not quantify the impact of unmodeled effects such as crosstalk, path-dependent latency, or calibration drift. In the revision we will include a new analysis section that (a) introduces bounded perturbations to gate fidelity and latency consistent with current experimental variability, (b) re-runs the circuit-level simulations under these perturbations, and (c) reports the resulting range of logical error rates together with a discussion of how the O(sqrt(n)) coupler scaling remains advantageous even under moderate degradation. This will directly address the robustness concern while preserving the manuscript’s central hardware-software co-design claims. revision: yes

Circularity Check

0 steps flagged

No circularity: architecture proposal and simulation results are independent of inputs

full rationale

The paper proposes a 2D toric oscillator network for routing BB codes, derives the O(sqrt(n)) coupler reduction from the layout geometry and routing algorithm, and reports simulated logical error rates from circuit-level noise modeling with external hardware parameters. No equations, predictions, or central claims reduce by construction to fitted inputs, self-definitions, or load-bearing self-citations. The derivation chain remains self-contained against the stated assumptions and external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 1 invented entities

The central claims rest on the realizability of the oscillator-based long-range gates and the fidelity of the noise model; these are domain assumptions without independent evidence supplied in the abstract.

free parameters (1)
  • noise model parameters
    Derived from experimental hardware parameters but not enumerated or justified in the abstract.
axioms (1)
  • domain assumption The 2D toric oscillator network provides scalable, high-fidelity long-range connectivity without introducing dominant new error sources.
    Invoked to support the reduction in couplers and low-latency operation.
invented entities (1)
  • programmable 2D toric network of oscillators no independent evidence
    purpose: Flexible communication fabric to enable long-range stabilizer measurements with O(sqrt(n)) couplers
    New architectural element introduced to solve connectivity constraints; no external validation provided.

pith-pipeline@v0.9.0 · 5603 in / 1501 out tokens · 52060 ms · 2026-05-10T04:42:17.925001+00:00 · methodology

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Reference graph

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