An automated predecoder generator for arbitrary qLDPC codes cuts decoder utilization by up to 3963x and supports hardware scaling to tens or hundreds of thousands of logical qubits within power limits.
Placing and routing quantum LDPC codes in multilayer superconducting hardware
5 Pith papers cite this work. Polarity classification is still indexing.
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abstract
Quantum error-correcting codes with asymptotically lower overheads than the surface code require nonlocal connectivity. Leveraging multilayer routing and long-range coupling capabilities in superconducting qubit hardware, we develop Hardware-Aware Layout, HAL: a robust, runtime-efficient heuristic algorithm that automates and optimizes the placement and routing of arbitrary codes. Using HAL, we generate around 150 explicit layouts of quantum low-density parity-check (qLDPC) codes with topological structure -- such as the bivariate bicycle codes and the open-boundary tile codes -- and find that removing the periodic boundaries significantly lowers the hardware complexity with only a moderate reduction of logical efficiency. We also lay out highly nonlocal qLDPC code families -- quantum radial and Tanner codes -- that achieve competitive tradeoffs between hardware complexity and logical efficiency. Based on our findings, we anticipate many novel qLDPC codes to be realizable on near-term superconducting qubit hardware and inform future directions for the co-design of quantum devices and fault-tolerant architectures.
citation-role summary
background 4
citation-polarity summary
fields
quant-ph 5years
2026 5roles
background 4representative citing papers
A 3D integrated transmon system achieves 99.87% single-qubit and 97.5% CZ gate fidelities with interchip entanglement, showing vertical tunable couplers enable scalable superconducting quantum processors.
The [[144,12,12]] bivariate bicycle code is distributed across 4 to 12 processors in a star network, with simulations showing logical error rates under varying nonlocal noise scaling.
A programmable 2D toric oscillator network enables efficient routing for bivariate bicycle LDPC codes, reducing long-range couplers to O(sqrt(n)) and achieving 3.06% logical error rate per cycle in simulations for the [[18,4,4]] code.
Geometry choices in bivariate-bicycle qLDPC syndrome extraction determine leading correlated error structure via weighted exposure, which correlates strongly with logical error rates and is reduced by biplanar layouts.
citing papers explorer
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Mitigating Classical Resource Costs in Quantum Error Correction via Generalized qLDPC Predecoding
An automated predecoder generator for arbitrary qLDPC codes cuts decoder utilization by up to 3963x and supports hardware scaling to tens or hundreds of thousands of logical qubits within power limits.
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Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system
A 3D integrated transmon system achieves 99.87% single-qubit and 97.5% CZ gate fidelities with interchip entanglement, showing vertical tunable couplers enable scalable superconducting quantum processors.
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Distributed Quantum Error Correction with Bivariate Bicycle Codes in a Modular Architecture
The [[144,12,12]] bivariate bicycle code is distributed across 4 to 12 processors in a star network, with simulations showing logical error rates under varying nonlocal noise scaling.
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Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures
A programmable 2D toric oscillator network enables efficient routing for bivariate bicycle LDPC codes, reducing long-range couplers to O(sqrt(n)) and achieving 3.06% logical error rate per cycle in simulations for the [[18,4,4]] code.
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Geometry-induced correlated noise in qLDPC syndrome extraction
Geometry choices in bivariate-bicycle qLDPC syndrome extraction determine leading correlated error structure via weighted exposure, which correlates strongly with logical error rates and is reduced by biplanar layouts.