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arxiv: 2605.11488 · v1 · submitted 2026-05-12 · 🪐 quant-ph

Recognition: 2 theorem links

· Lean Theorem

Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system

Xudong Liao , Shuyi Pan , Zhenxing Zhang , Sainan Huai , Zhiwen Zong , Xiaopei Yang , Kunliang Bu , Wen Zheng
show 6 more authors
Xinsheng Tan Yang Yu Yuan Li Yi-Cong Zheng Tianqi Cai Shengyu Zhang
Authors on Pith no claims yet

Pith reviewed 2026-05-13 02:12 UTC · model grok-4.3

classification 🪐 quant-ph
keywords 3D integrationvertical tunable couplersuperconducting transmon qubitsflip-chip bondinginterchip couplingquantum entanglementscalable quantum processors
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The pith

Vertical tunable couplers connect stacked transmon chips in a 3D processor while keeping gate fidelities high.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates a three-dimensional integrated superconducting quantum processor formed by stacking two qubit chips on opposite sides of a carrier chip and bonding them with multilayer flip-chip technology. Planar tunable couplers handle coupling within each chip, while vertical tunable couplers in the carrier chip enable controllable interactions between chips. Randomized benchmarking shows single-qubit gates at 99.87 percent fidelity with negligible crosstalk and controlled-Z gates at 97.5 percent average fidelity for both intra-chip and inter-chip operations. The system also prepares high-fidelity Bell states and a coherent four-qubit W state across chips. A reader would care because this approach directly addresses the physical size limits of planar chips, offering a concrete route to larger processors required for fault-tolerant quantum computation.

Core claim

In a 3D integrated transmon system, two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding, with vertical tunable couplers embedded in the carrier chip mediating interchip coupling that achieves simultaneous single-qubit gate fidelities of 99.87 percent and controlled-Z gate fidelities of 97.5 percent for both intrachip and interchip operations, together with coherent interchip entanglement distribution shown by Bell-state preparation and a four-qubit W state.

What carries the argument

Vertical tunable coupler embedded in the carrier chip, which provides controllable interchip qubit interactions in the multilayer flip-chip bonded stack.

If this is right

  • Intrachip and interchip controlled-Z gates reach the same 97.5 percent average fidelity, indicating no performance penalty from the vertical link.
  • Simultaneous single-qubit operations across chips maintain 99.87 percent fidelity with negligible crosstalk.
  • The architecture supports coherent multi-qubit entanglement distributed across separate chips, including a four-qubit W state.
  • Vertical coupling provides a scalable alternative to planar architectures for building larger quantum processors.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Independent fabrication and testing of separate chips before assembly could reduce yield issues in large processors.
  • The demonstrated low crosstalk opens the possibility of denser 3D qubit layouts than planar designs allow.
  • Extending the stack to three or more chips could test whether the same fidelity levels hold for deeper vertical connectivity.

Load-bearing premise

The multilayer flip-chip bonding and vertical tunable couplers introduce negligible additional decoherence, loss, or crosstalk that would block scaling to error-corrected regimes.

What would settle it

A direct measurement showing qubit coherence times or gate error rates degrading substantially when the number of stacked chips or total qubit count increases beyond the demonstrated two-chip device.

Figures

Figures reproduced from arXiv: 2605.11488 by Kunliang Bu, Sainan Huai, Shengyu Zhang, Shuyi Pan, Tianqi Cai, Wen Zheng, Xiaopei Yang, Xinsheng Tan, Xudong Liao, Yang Yu, Yi-Cong Zheng, Yuan Li, Zhenxing Zhang, Zhiwen Zong.

Figure 1
Figure 1. Figure 1: FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3 [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
read the original abstract

Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit $W$ state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript demonstrates a 3D integrated superconducting quantum processor in which two transmon qubit chips are vertically stacked on opposite sides of a carrier chip and connected via multilayer flip-chip bonding. Intrachip coupling is handled by planar tunable couplers while interchip coupling uses vertical tunable couplers embedded in the carrier. Randomized benchmarking yields simultaneous single-qubit gate fidelities of 99.87% with negligible crosstalk, controlled-Z gates achieve 97.5% average fidelity for both intra- and inter-chip operations, and the work includes high-fidelity Bell-state preparation together with coherent generation of a four-qubit W state.

Significance. If the central experimental claims are substantiated, the work would be significant for superconducting quantum hardware because it provides a concrete demonstration of vertical integration that increases connectivity options beyond planar limits. The reported inter-chip CZ fidelity and entanglement distribution are competitive and directly relevant to modular or 3D architectures. Credit is due for the experimental realization of galvanic vertical tunable couplers and the simultaneous operation of intra- and inter-chip gates on the same device. However, the significance for fault-tolerant scaling remains conditional on showing that the added 3D elements do not introduce prohibitive decoherence or crosstalk at larger scales.

major comments (2)
  1. Abstract: The abstract states concrete fidelities (99.87% single-qubit RB, 97.5% CZ) and state-preparation results but supplies no information on calibration procedures, statistical error analysis, data exclusion criteria, or full device parameters. These omissions make it impossible to assess whether the quoted numbers reliably support the claim of negligible crosstalk and high-fidelity inter-chip operation.
  2. Abstract and main results: The assertion that vertical coupling constitutes a promising pathway toward QEC-compatible scaling rests on the premise that multilayer flip-chip bonding and carrier-embedded vertical couplers add negligible decoherence, loss, or crosstalk. No quantitative comparison of T1/T2 times or ZZ crosstalk is presented between the 3D stack and an otherwise identical planar control device, nor is any data shown on how bonding yield or parameter spread scales with array size. This comparison is load-bearing for the central claim.
minor comments (1)
  1. The manuscript would benefit from a consolidated table listing all measured device parameters, coherence times, and gate metrics with uncertainties for both intra- and inter-chip elements.

Simulated Author's Rebuttal

2 responses · 2 unresolved

We thank the referee for the careful review and constructive comments. We address each major comment below and have revised the manuscript to improve clarity and temper claims where the supporting data are limited.

read point-by-point responses

  1. Referee: Abstract: The abstract states concrete fidelities (99.87% single-qubit RB, 97.5% CZ) and state-preparation results but supplies no information on calibration procedures, statistical error analysis, data exclusion criteria, or full device parameters. These omissions make it impossible to assess whether the quoted numbers reliably support the claim of negligible crosstalk and high-fidelity inter-chip operation.

    Authors: We agree that the abstract, being concise, does not contain these details. The full manuscript reports calibration procedures in Section II, statistical uncertainties and data exclusion in the Supplementary Information, and device parameters in Table I and the Methods. To address the concern, we have revised the abstract to specify that fidelities were extracted via simultaneous randomized benchmarking and cross-entropy benchmarking, and we now explicitly direct readers to the relevant sections for calibration, error analysis, and crosstalk characterization. This keeps the abstract at an appropriate length while improving traceability. revision: yes

  2. Referee: Abstract and main results: The assertion that vertical coupling constitutes a promising pathway toward QEC-compatible scaling rests on the premise that multilayer flip-chip bonding and carrier-embedded vertical couplers add negligible decoherence, loss, or crosstalk. No quantitative comparison of T1/T2 times or ZZ crosstalk is presented between the 3D stack and an otherwise identical planar control device, nor is any data shown on how bonding yield or parameter spread scales with array size. This comparison is load-bearing for the central claim.

    Authors: We acknowledge that a direct comparison to an otherwise identical planar control device fabricated in the same process run is absent and would strengthen the argument. In the revised manuscript we have added a discussion paragraph comparing our measured T1 (∼60 μs) and T2 (∼40 μs) times and ZZ crosstalk levels to recent literature values for planar tunable-coupler devices; the numbers are competitive but not identical-run data. We have also changed the abstract and conclusion language from “establish” to “suggest” that vertical coupling is a promising pathway, making the claim appropriately cautious. Data on bonding yield and parameter spread versus array size are not available in this small-scale (four-qubit) demonstration and would require a separate scaling study. revision: partial

standing simulated objections not resolved
  • Direct experimental comparison of T1/T2 and ZZ crosstalk against an identical planar control device fabricated in the same run
  • Quantitative data on bonding yield or parameter spread as a function of array size

Circularity Check

0 steps flagged

No circularity: experimental demonstration with direct measurements

full rationale

The manuscript is an experimental report on device fabrication, gate characterization via randomized benchmarking, and entanglement generation in a 3D stacked transmon architecture. No derivation chain, first-principles calculation, or predictive model is presented that could reduce to fitted inputs, self-definitions, or self-citations. All reported metrics (fidelities, Bell states, W-state generation) are obtained from direct measurement on the fabricated device; the interpretation that vertical coupling is promising for scaling is an empirical conclusion, not a mathematical result forced by construction. The work is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

This is an experimental demonstration paper. The central claim rests on successful fabrication and measurement rather than new theoretical constructs or fitted parameters.

axioms (1)
  • domain assumption Standard assumptions of superconducting transmon physics, including coherence limited by known loss channels and flip-chip bonding preserving qubit quality factors.
    The reported fidelities and entanglement generation implicitly rely on these holding for the fabricated devices.

pith-pipeline@v0.9.0 · 5509 in / 1243 out tokens · 47502 ms · 2026-05-13T02:12:07.685065+00:00 · methodology

discussion (0)

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