A centralized EVU-APMU hardware architecture collects and processes performance counter data on a dedicated side processor, demonstrated on a RISC-V SoC for memory regulation and function-level profiling.
Denial-of-Service Attacks on Shared Cache in Multicore: Analysis and Prevention
1 Pith paper cite this work. Polarity classification is still indexing.
abstract
In this paper we investigate the feasibility of denial-of-service (DoS) attacks on shared caches in multicore platforms. With carefully engineered attacker tasks, we are able to cause more than 300X execution time increases on a victim task running on a dedicated core on a popular embedded multicore platform, regardless of whether we partition its shared cache or not. Based on careful experimentation on real and simulated multicore platforms, we identify an internal hardware structure of a non-blocking cache, namely the cache writeback buffer, as a potential target of shared cache DoS attacks. We propose an OS-level solution to prevent such DoS attacks by extending a state-of-the-art memory bandwidth regulation mechanism. We implement the proposed mechanism in Linux on a real multicore platform and show its effectiveness in protecting against cache DoS attacks.
citation-role summary
citation-polarity summary
fields
cs.AR 1years
2026 1verdicts
CONDITIONAL 1roles
background 1polarities
background 1representative citing papers
citing papers explorer
-
A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
A centralized EVU-APMU hardware architecture collects and processes performance counter data on a dedicated side processor, demonstrated on a RISC-V SoC for memory regulation and function-level profiling.