RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
Make every move count: Llm-based high-quality rtl code generation using mcts
6 Pith papers cite this work. Polarity classification is still indexing.
6
Pith papers citing it
representative citing papers
ARIADNE combines blackboard architecture with MCTS to coordinate strategy, code, test, evaluation, and repair stages, yielding higher Pass@1 scores than prior LLM baselines on APPS, CodeContests, and related benchmarks.
Dr. RTL's multi-agent framework with group-relative skill learning achieves 21% WNS and 17% TNS timing improvements plus 6% area reduction on 20 real-world RTL designs over commercial synthesis tools.
ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.
UVM^2 is an LLM-driven system that generates and refines UVM testbenches for RTL verification, reporting up to substantial time savings and average code/function coverage of 87.44%/89.58% on designs up to 1.6K lines, outperforming prior methods.
A survey of LLM applications in electronic design automation and hardware security, covering opportunities, vulnerabilities, and countermeasures.
citing papers explorer
-
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.