AutoVeriFix improves LLM-generated Verilog functional correctness by generating a high-level Python reference model, deriving a high-coverage testbench, and iteratively fixing Verilog simulation mismatches.
Benchmarking large language models for automated verilog rtl code generation,
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AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
AutoVeriFix improves LLM-generated Verilog functional correctness by generating a high-level Python reference model, deriving a high-coverage testbench, and iteratively fixing Verilog simulation mismatches.