Running standard wireless kernels on the RISC-V Ara vector processor shows that longer vector registers cut clock-cycle counts.
Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension
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Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication
Running standard wireless kernels on the RISC-V Ara vector processor shows that longer vector registers cut clock-cycle counts.