RefEvo achieves 95% pass rate on 20 hardware modules for SystemC reference model generation using dynamic multi-agent planning, co-evolutionary verification, and spec anchoring, with 71% token reduction.
Chatcpu: An agile cpu design and verification platform with llm
2 Pith papers cite this work. Polarity classification is still indexing.
2
Pith papers citing it
years
2026 2verdicts
UNVERDICTED 2representative citing papers
VeriGraphi introduces a knowledge-graph-anchored multi-agent pipeline that produces reliable hierarchical synthesizable Verilog for complex designs such as RISC-V processors.
citing papers explorer
-
RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation
RefEvo achieves 95% pass rate on 20 hardware modules for SystemC reference model generation using dynamic multi-agent planning, co-evolutionary verification, and spec anchoring, with 71% token reduction.
-
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
VeriGraphi introduces a knowledge-graph-anchored multi-agent pipeline that produces reliable hierarchical synthesizable Verilog for complex designs such as RISC-V processors.