CMOS field-programmable spiking neural network with LIF neurons, integrated VCOs, and on-chip FPGA implements hardware reservoir computing, demonstrated via FORCE learning and NARMA10 tasks with 21.7 pJ/pulse energy and 540 NAND2 area per neuron.
Convolutional networks for fast, energy-efficient neuromorphic computing
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Digital neuromorphic chips encounter a new memory wall as on-chip memories dominate area and energy use, limiting competitiveness in edge applications without reorganized memory architectures.
citing papers explorer
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CMOS Implementation of Field Programmable Spiking Neural Network for Hardware Reservoir Computing
CMOS field-programmable spiking neural network with LIF neurons, integrated VCOs, and on-chip FPGA implements hardware reservoir computing, demonstrated via FORCE learning and NARMA10 tasks with 21.7 pJ/pulse energy and 540 NAND2 area per neuron.
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Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing
Digital neuromorphic chips encounter a new memory wall as on-chip memories dominate area and energy use, limiting competitiveness in edge applications without reorganized memory architectures.