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arxiv: 2604.08774 · v1 · submitted 2026-04-09 · 💻 cs.AR · cs.NE

Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing

Amirreza Yousefzadeh , Sameed Sohail , Ana Lucia Varbanescu This is my paper

Pith reviewed 2026-05-10 16:59 UTC · model grok-4.3

classification 💻 cs.AR cs.NE
keywords neuromorphic computingmemory walldigital processorson-chip memorySRAMSTT-MRAMedge computingembedded systems
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The pith

Digital neuromorphic processors create a new memory wall as on-chip SRAM and STT-MRAM dominate area and energy.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Neuromorphic designs aim to remove the classic von Neumann memory wall by distributing computation close to memory. The paper reviews multiple digital neuromorphic processors and finds that on-chip memory systems, especially SRAM and emerging STT-MRAM, now consume the largest shares of silicon area and power. This reversal produces a fresh bottleneck that the authors argue will hinder effective use in power-limited edge and embedded applications. A reader would care because it questions whether current neuromorphic hardware can meet its efficiency goals without changes to memory layout. The work closes by outlining research directions for better memory organization.

Core claim

Analysis of energy and area efficiency across selected digital neuromorphic processors shows that on-chip memory, including SRAM and STT-MRAM, has become the dominant consumer, forming a new memory wall that may prevent these processors from competing in edge applications unless memory organization is re-evaluated.

What carries the argument

Critical comparison of area and energy costs of on-chip memory technologies within distributed digital neuromorphic architectures.

If this is right

  • Digital neuromorphic processors will struggle to compete in edge and embedded applications.
  • Re-evaluation of memory organization is required before these systems can scale effectively.
  • Emerging memories such as STT-MRAM still contribute to the dominance of on-chip costs rather than solving them.
  • Future designs must explore new memory organizations to remove the fresh bottleneck.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same memory overhead pattern may appear in other non-von Neumann hardware beyond the digital neuromorphic class examined here.
  • Adoption rates for neuromorphic chips in IoT and mobile devices could remain low until memory integration improves.
  • Designers could test whether hybrid on-chip and off-chip memory splits change overall system efficiency in practice.

Load-bearing premise

The energy and area patterns seen in the chosen processors and memory technologies will hold for digital neuromorphic designs in general and will block competitive edge performance without major redesign.

What would settle it

Publication of a digital neuromorphic chip for edge tasks where on-chip memory uses less than 30 percent of total area and less than 40 percent of energy while maintaining claimed performance would falsify the new memory wall as a general barrier.

Figures

Figures reproduced from arXiv: 2604.08774 by Amirreza Yousefzadeh, Ana Lucia Varbanescu, Sameed Sohail.

Figure 1
Figure 1. Figure 1: The trade-off between area efficiency and energy consumption in [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Fully distributed memory (mem) and processing elements (PE) in [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Spatial mapping of the layers of a neural network onto tiled memory [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
read the original abstract

The rapid advancement of neuromorphic technology aims to address the memory wall challenge inherent in conventional von Neumann architectures. This paper critically examines current digital neuromorphic processors and their strategies to mitigate this bottleneck. While designed to bring computation closer to memory through distributed architectures, our findings indicate that on-chip memory systems, including SRAM and emerging technologies like STT-MRAM, have become significant consumers of area and energy, leading to a new memory wall. Through an analysis of energy and area efficiency in various memory technologies, we argue that without a re-evaluation of memory organization, digital neuromorphic processors may struggle to compete effectively in edge and embedded applications. We conclude with potential pathways for future research to overcome the limitations of on-chip memory in neuromorphic systems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper critically examines digital neuromorphic processors and their distributed architectures intended to mitigate the von Neumann memory wall. It argues that on-chip memory systems (SRAM and emerging technologies such as STT-MRAM) have become dominant consumers of area and energy, thereby creating a new memory wall. Through an analysis of energy and area efficiency across selected memory technologies, the manuscript concludes that without re-evaluation of memory organization, these processors will struggle to compete in edge and embedded applications, and it outlines potential future research pathways.

Significance. If the quantitative analysis proves representative and the efficiency comparisons hold under broader sampling, the result would be significant for neuromorphic hardware design by identifying a persistent on-chip memory bottleneck that could limit scalability and energy efficiency at the edge. The work usefully redirects attention from computation-centric optimizations to memory organization as the load-bearing constraint.

major comments (2)
  1. [Abstract] Abstract: the central claim that on-chip memory systems have become significant consumers of area and energy (creating a new memory wall) rests on an analysis of energy and area efficiency, yet the abstract supplies no quantitative results, data tables, methods, or specific processor examples to substantiate the magnitude or generality of this dominance.
  2. [Abstract] Abstract: the generalization from the examined processors and memory technologies (SRAM, STT-MRAM) to the broader class of digital neuromorphic designs is asserted without evidence of representativeness, such as coverage statistics, systematic sampling across core counts/sparsity/technology nodes, or sensitivity checks. This step is load-bearing for the conclusion that the new memory wall will prevent effective competition in edge applications.
minor comments (1)
  1. [Abstract] The abstract would benefit from a single sentence naming the specific processors or technology nodes analyzed, to allow readers to gauge scope immediately.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below with point-by-point responses and indicate planned revisions to strengthen the presentation.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that on-chip memory systems have become significant consumers of area and energy (creating a new memory wall) rests on an analysis of energy and area efficiency, yet the abstract supplies no quantitative results, data tables, methods, or specific processor examples to substantiate the magnitude or generality of this dominance.

    Authors: We agree that the abstract, as a concise summary, omits specific quantitative results and examples. The full manuscript contains detailed energy and area breakdowns, including comparisons across SRAM and STT-MRAM in representative processors, supported by figures and tables. To better ground the central claim, we will revise the abstract to incorporate key quantitative highlights (e.g., observed memory dominance percentages) and reference specific processor examples while preserving its brevity. revision: yes

  2. Referee: [Abstract] Abstract: the generalization from the examined processors and memory technologies (SRAM, STT-MRAM) to the broader class of digital neuromorphic designs is asserted without evidence of representativeness, such as coverage statistics, systematic sampling across core counts/sparsity/technology nodes, or sensitivity checks. This step is load-bearing for the conclusion that the new memory wall will prevent effective competition in edge applications.

    Authors: The analysis draws on prominent, well-documented digital neuromorphic processors from the recent literature that span varying core counts, memory technologies, and technology nodes to illustrate the emerging trend. A exhaustive statistical sampling is not feasible given the limited number of fabricated designs in this emerging field. We will add an explicit discussion of selection criteria and scope limitations (e.g., in the introduction or a dedicated subsection) to justify the generalization and acknowledge boundaries, thereby addressing the concern without overclaiming universality. revision: partial

Circularity Check

0 steps flagged

No significant circularity; purely observational critique with no derivations or self-referential modeling

full rationale

The paper contains no equations, fitted parameters, or derivation chains. Its central claim rests on an observational analysis of selected existing processors and memory technologies (SRAM, STT-MRAM) to argue that on-chip memory now dominates area/energy. This is a direct critique of published hardware data rather than any self-definitional loop, fitted-input prediction, or load-bearing self-citation that reduces the conclusion to its own inputs by construction. The argument is therefore self-contained against external benchmarks and receives the default non-circularity finding.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only view reveals no explicit free parameters, axioms, or invented entities; the argument relies on standard domain concepts of memory wall and neuromorphic design without introducing new postulates.

pith-pipeline@v0.9.0 · 5428 in / 1091 out tokens · 34604 ms · 2026-05-10T16:59:55.507281+00:00 · methodology

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Reference graph

Works this paper leans on

21 extracted references · 21 canonical work pages

  1. [1]

    Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design,

    G. Tang, A. Safa, K. Shidqi, P. Detterer, S. Traferro, M. Konijnenburg, M. Sifalakis, G.-J. van Schaik, and A. Yousefzadeh, “Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design,” in2023 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2023, pp. 1–5

    work page 2023

  2. [2]

    Hitting the memory wall: Implications of the obvious,

    W. A. Wulf and S. A. McKee, “Hitting the memory wall: Implications of the obvious,”ACM SIGARCH computer architecture news, vol. 23, no. 1, pp. 20–24, 1995

    work page 1995

  3. [3]

    Seneca: building a fully digital neuromorphic processor, design trade-offs and challenges,

    G. Tang, K. Vadivel, Y . Xu, R. Bilgic, K. Shidqi, P. Detterer, S. Traferro, M. Konijnenburg, M. Sifalakis, G.-J. van Schaiket al., “Seneca: building a fully digital neuromorphic processor, design trade-offs and challenges,” Frontiers in Neuroscience, vol. 17, p. 1187252, 2023

    work page 2023

  4. [4]

    Convolutional networks for fast, energy-efficient neuromorphic computing,

    S. K. Esser, P. A. Merolla, J. V . Arthur, A. S. Cassidy, R. Appuswamy, A. Andreopoulos, D. J. Berg, J. L. McKinstry, T. Melano, D. R. Barch, C. di Nolfo, P. Datta, A. Amir, B. Taba, M. D. Flickner, and D. S. Modha, “Convolutional networks for fast, energy-efficient neuromorphic computing,”Proceedings of the National Academy of Sciences, vol. 113, no. 41,...

    work page doi:10.1073/pnas.1604850113 2016

  5. [5]

    Nxtf: An api and compiler for deep spiking neural networks on intel loihi,

    B. Rueckauer, C. Bybee, R. Goettsche, Y . Singh, J. Mishra, and A. Wild, “Nxtf: An api and compiler for deep spiking neural networks on intel loihi,”ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, no. 3, pp. 1–22, 2022

    work page 2022

  6. [6]

    Arts: An adaptive regularization training schedule for activation sparsity exploration,

    Z. Zhu, A. Pourtaherian, L. Waeijen, L. Bamberg, E. Bondarev, and O. Moreira, “Arts: An adaptive regularization training schedule for activation sparsity exploration,” in2022 25th Euromicro Conference on Digital System Design (DSD). IEEE, 2022, pp. 415–422

    work page 2022

  7. [7]

    Speck: A smart event-based vision sensor with a low latency 327k neuron convolutional neuronal network processing pipeline,

    O. Richter, Y . Xing, M. De Marchi, C. Nielsen, M. Katsimpris, R. Catta- neo, Y . Ren, Y . Hu, Q. Liu, S. Sheiket al., “Speck: A smart event-based vision sensor with a low latency 327k neuron convolutional neuronal network processing pipeline,”arXiv preprint arXiv:2304.06793, 2023

    work page arXiv 2023

  8. [8]

    Trip: Trainable region-of- interest prediction for hardware-efficient neuromorphic processing on event-based vision,

    C. Arjmand, Y . Xu, K. Shidqi, A. F. Dobrita, K. Vadivel, P. Detterer, M. Sifalakis, A. Yousefzadeh, and G. Tang, “Trip: Trainable region-of- interest prediction for hardware-efficient neuromorphic processing on event-based vision,” in2024 International Conference on Neuromorphic Systems (ICONS). IEEE, 2024, pp. 94–101

    work page 2024

  9. [9]

    Sparse convolutional recurrent learning for efficient event-base neuromorphic object detection,

    S. Wang andet al., “Sparse convolutional recurrent learning for efficient event-base neuromorphic object detection,” inIJCNN. IEEE, 2025

    work page 2025

  10. [10]

    Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration,

    Y . Xu, K. Shidqi, G.-J. van Schaik, R. Bilgic, A. Dobrita, S. Wang, R. Meijer, P. Nembhani, C. Arjmand, P. Martinelloet al., “Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration,”Frontiers in Neuroscience, vol. 18, p. 1335422, 2024

    work page 2024

  11. [11]

    Non-uniform memory partitioning for low-power spiking neural networks,

    S. Richter andet al., “Non-uniform memory partitioning for low-power spiking neural networks,” inAICAS. IEEE, 2025

    work page 2025

  12. [12]

    et al.: The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing (Aug 2022), arXiv:2103.08392 [cs]

    S. H ¨oppner, Y . Yan, A. Dixius, S. Scholze, J. Partzsch, M. Stolba, F. Kelber, B. V ogginger, F. Neum ¨arker, G. Ellguthet al., “The spin- naker 2 processing element architecture for hybrid digital neuromorphic computing,”arXiv preprint arXiv:2103.08392, 2021

    work page arXiv 2021

  13. [13]

    The spinnaker project,

    S. B. Furber, F. Galluppi, S. Temple, and L. A. Plana, “The spinnaker project,”Proceedings of the IEEE, vol. 102, no. 5, pp. 652–665, 2014

    work page 2014

  14. [14]

    Performance comparison of time- step-driven versus event-driven neural state update approaches in spin- naker,

    A. Yousefzadeh, M. Soto, T. Serrano-Gotarredona, F. Galluppi, L. Plana, S. Furber, and B. Linares-Barranco, “Performance comparison of time- step-driven versus event-driven neural state update approaches in spin- naker,” in2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018, pp. 1–4

    work page 2018

  15. [15]

    Sensim: An event- driven parallel simulator for multi-core neuromorphic systems,

    P. Nembhani, K. Vadivel, G. Tang, M. Tahghighi, G.-J. van Schaik, M. Sifalakis, Z. Al-Ars, and A. Yousefzadeh, “Sensim: An event- driven parallel simulator for multi-core neuromorphic systems,” in2024 International Joint Conference on Neural Networks (IJCNN). IEEE, 2024, pp. 1–6

    work page 2024

  16. [16]

    Tutorial on memristor-based computing for smart edge applications,

    A. Gebregiorgis, A. Singh, A. Yousefzadeh, D. Wouters, R. Bishnoi, F. Catthoor, and S. Hamdioui, “Tutorial on memristor-based computing for smart edge applications,”Memories-Materials, Devices, Circuits and Systems, vol. 4, p. 100025, 2023

    work page 2023

  17. [17]

    Crossbar-constrained technology mapping for reram based in-memory computing,

    D. Bhattacharjee, Y . Tavva, A. Easwaran, and A. Chattopadhyay, “Crossbar-constrained technology mapping for reram based in-memory computing,”IEEE Transactions on Computers, vol. 69, no. 5, pp. 734– 748, 2020

    work page 2020

  18. [18]

    Hermes-core—a 1.59-tops/mm 2 pcm on 14-nm cmos in-memory compute core using 300-ps/lsb linearized cco-based adcs,

    R. Khaddam-Aljameh, M. Stanisavljevic, J. F. Mas, G. Karunaratne, M. Br ¨andli, F. Liu, A. Singh, S. M. M ¨uller, U. Egger, A. Petropoulos et al., “Hermes-core—a 1.59-tops/mm 2 pcm on 14-nm cmos in-memory compute core using 300-ps/lsb linearized cco-based adcs,”IEEE Journal of Solid-State Circuits, vol. 57, no. 4, pp. 1027–1038, 2022

    work page 2022

  19. [19]

    A critical assessment of dram-pim architectures-trends, challenges and solutions,

    C. Sudarshan, M. H. Sadi, L. Steiner, C. Weis, and N. Wehn, “A critical assessment of dram-pim architectures-trends, challenges and solutions,” inInternational Conference on Embedded Computer Systems. Springer, 2022, pp. 362–379

    work page 2022

  20. [20]

    Multidie 3-d stacking of memory dominated neuromorphic architec- tures,

    L. M. G. Rocha, R. Bilgic, M. Naeim, S. Das, H. Oprins, A. Youse- fzadeh, M. Konijnenburg, D. Milojevic, J. Myers, J. Ryckaertet al., “Multidie 3-d stacking of memory dominated neuromorphic architec- tures,”IEEE Transactions on V ery Large Scale Integration (VLSI) Systems, 2024

    work page 2024

  21. [21]

    A hybrid memristor/cmos snn for implementing one-shot winner-takes-all training,

    J. Ahmadi-Farsani, S. Ricci, S. Hashemkhani, D. Ielmini, B. Linares- Barranco, and T. Serrano-Gotarredona, “A hybrid memristor/cmos snn for implementing one-shot winner-takes-all training,” in2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2022, pp. 210–214

    work page 2022