A RISC-V-controlled self-calibration technique in a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI improves compute SNR by 25-45% to reach 18-24 dB.
A 40-nm 118.44-TOPS/W V oltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi- Bit Encoding,
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Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration
A RISC-V-controlled self-calibration technique in a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI improves compute SNR by 25-45% to reach 18-24 dB.