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arxiv: 2506.15440 · v1 · submitted 2025-06-18 · 💻 cs.AR

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration

Omar Numan , Gaurav Singh , Kazybek Adam , Jelin Leslin , Aleksi Korsman , Otto Simola , Marko Kosunen , Jussi Ryyn\"anen
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Martin Andraud
This is my paper

Pith reviewed 2026-05-19 09:14 UTC · model grok-4.3

classification 💻 cs.AR
keywords compute-in-memorymixed-signal CIMRISC-V calibrationself-calibrationanalog variation compensationSNR improvement22 nm FDSOIresistive memory
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The pith

RISC-V controlled on-chip calibration raises mixed-signal CIM compute SNR by 25 to 45 percent to reach 18-24 dB.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates a mixed-signal compute-in-memory accelerator fabricated in 22 nm FDSOI that stores weights in SRAM while performing multi-bit operations with linear resistors. An integrated RISC-V processor runs an automated calibration routine that compensates for analog variations across different columns. This compensation lifts signal-to-noise ratio enough to support reliable computation for AI workloads. The design also supplies an open-source interface for programming and testing the CIM system. The same calibration approach is shown to extend to newer high-density resistor technologies for higher performance.

Core claim

The central claim is that embedding a RISC-V core to drive on-chip self-calibration in a resistive mixed-signal CIM SoC compensates analog variations, improving compute SNR by 25 to 45 percent across columns and reaching 18-24 dB while combining SRAM density with multi-bit resistive computation in a single 22 nm FDSOI chip.

What carries the argument

RISC-V controlled on-chip calibration routine that identifies and compensates analog variations in the resistive CIM columns.

If this is right

  • SRAM-based weight storage paired with linear resistors enables both density and multi-bit accuracy in one CIM core.
  • Integration with an open-source RISC-V processor supplies a practical path to end-to-end AI acceleration on the SoC.
  • The calibration method supports extension to emerging high-density linear resistor technologies for improved energy or speed.
  • Reliable 18-24 dB SNR makes mixed-signal CIM cores more viable for production AI inference hardware.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Production chips could ship with built-in calibration that removes the need for external test equipment at volume.
  • The same control loop might be reused to track aging or temperature drift during field operation.
  • Open-source programming interfaces could shorten the time for other groups to adopt similar calibrated CIM designs.

Load-bearing premise

The automated calibration routine driven by the RISC-V core can reliably detect and correct analog variations across columns without introducing new systematic errors or needing per-chip manual tuning.

What would settle it

Fabricate multiple chips, run the RISC-V calibration routine on each, measure compute SNR before and after on the same columns, and check whether the reported 25-45 percent gain appears consistently without extra off-chip adjustments.

Figures

Figures reproduced from arXiv: 2506.15440 by Aleksi Korsman, Gaurav Singh, Jelin Leslin, Jussi Ryyn\"anen, Kazybek Adam, Marko Kosunen, Martin Andraud, Omar Numan, Otto Simola.

Figure 1
Figure 1. Figure 1: Key sources of non-idealities in resistive-based CIM cores: DAC [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Proof-of-concept Acore-CIM SoC composed of a 32-bit RISC-V core controlling a [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) 6-bit R-2R MDAC Input DAC Cell with an extra sign bit for [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: MDAC Weight Cell (MWC) schematic: Uses an R-2R MDAC with [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Illustration of the open-source simulation framework of the proposed [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Error distributions for a selected CIM column during characterization [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Uncalibrated MAC outputs across CIM columns. (b) Extracted per-column gain ( [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: A comparison of spatial variation enhancement across CIM columns [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Compute SNR boost across CIM columns with BISC, achieving an [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
read the original abstract

Developing accurate and reliable Compute-In-Memory (CIM) architectures is becoming a key research focus to accelerate Artificial Intelligence (AI) tasks on hardware, particularly Deep Neural Networks (DNNs). In that regard, there has been significant interest in analog and mixed-signal CIM architectures aimed at increasing the efficiency of data storage and computation to handle the massive amount of data needed by DNNs. Specifically, resistive mixed-signal CIM cores are pushed by recent progresses in emerging Non-Volatile Memory (eNVM) solutions. Yet, mixed-signal CIM computing cores still face several integration and reliability challenges that hinder their large-scale adoption into end-to-end AI computing systems. In terms of integration, resistive and eNVM-based CIM cores need to be integrated with a control processor to realize end-to-end AI acceleration. Moreover, SRAM-based CIM architectures are still more efficient and easier to program than their eNVM counterparts. In terms of reliability, analog circuits are more susceptible to variations, leading to computation errors and degraded accuracy. This work addresses these two challenges by proposing a self-calibrated mixed-signal CIM accelerator SoC, fabricated in 22-nm FDSOI technology. The integration is facilitated by (1) the CIM architecture, combining the density and ease of SRAM-based weight storage with multi-bit computation using linear resistors, and (2) an open-source programming and testing strategy for CIM systems. The accuracy and reliability are enabled through an automated RISC-V controlled on-chip calibration, allowing us to improve the compute SNR by 25 to 45% across multiple columns to reach 18-24 dB. To showcase further integration possibilities, we show how our proof-of-concept SoC can be extended to recent high-density linear resistor technologies for enhanced computing performance.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents Acore-CIM, a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI technology. It combines SRAM-based weight storage with linear resistors for multi-bit analog computation, integrates an open-source RISC-V core for control and testing, and introduces an automated on-chip self-calibration routine to mitigate analog variations. The central result is a reported 25-45% improvement in compute SNR across columns, reaching 18-24 dB, with additional discussion on extending the approach to high-density resistor technologies for better performance.

Significance. If the on-chip calibration proves robust, reproducible across dies, and free of new systematic errors, the work would meaningfully advance practical mixed-signal CIM systems for DNN acceleration by solving both processor integration and variation-induced reliability issues. The SRAM-plus-resistor architecture and RISC-V-driven open-source flow are practical strengths that could aid adoption. The SNR gains, if supported by adequate experimental statistics, would provide useful evidence for the viability of calibrated analog CIM cores.

major comments (2)
  1. The automated RISC-V-controlled calibration routine is load-bearing for the reliability claims yet is described only at a high level. No algorithm, pseudocode, or step-by-step sequence is provided showing how column-specific offsets and gains are identified using solely on-chip resources, how reference signals are generated, or how coefficients are stored and applied without introducing bias from RISC-V timing jitter or reference drift.
  2. The reported SNR improvements (25-45% to 18-24 dB) lack supporting experimental details. No information is given on the number of chips tested, measurement conditions, error bars, or statistical analysis, which is required to substantiate that the gains are achieved reproducibly without per-device manual tuning.
minor comments (1)
  1. The abstract and introduction could more explicitly distinguish the contributions of the resistor-based computation from the calibration routine to clarify the source of the SNR gains.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback on our manuscript. We address each major comment below and will revise the manuscript to provide the requested clarifications and additional details.

read point-by-point responses

  1. Referee: The automated RISC-V-controlled calibration routine is load-bearing for the reliability claims yet is described only at a high level. No algorithm, pseudocode, or step-by-step sequence is provided showing how column-specific offsets and gains are identified using solely on-chip resources, how reference signals are generated, or how coefficients are stored and applied without introducing bias from RISC-V timing jitter or reference drift.

    Authors: We agree that the current high-level description of the calibration routine limits reproducibility. In the revised manuscript we will add a dedicated section with the full algorithm, pseudocode, and a step-by-step sequence that explains how column-specific offsets and gains are determined using only on-chip resources, how reference signals are generated, and how coefficients are stored and applied. We will also add explicit discussion of how the implementation avoids systematic bias from RISC-V timing jitter and reference drift, supported by our measured results. revision: yes

  2. Referee: The reported SNR improvements (25-45% to 18-24 dB) lack supporting experimental details. No information is given on the number of chips tested, measurement conditions, error bars, or statistical analysis, which is required to substantiate that the gains are achieved reproducibly without per-device manual tuning.

    Authors: We acknowledge that the experimental section currently lacks the requested statistics. In the revised manuscript we will expand the results to report the number of chips measured, the precise measurement conditions, error bars on the SNR values, and the statistical analysis performed. These additions will demonstrate that the reported 25-45% SNR gains are reproducible across devices without per-device manual tuning. revision: yes

Circularity Check

0 steps flagged

No significant circularity; results are empirical silicon measurements

full rationale

The paper describes a fabricated mixed-signal CIM SoC in 22-nm FDSOI with an RISC-V-driven on-chip calibration routine. The central performance claims (25-45% SNR improvement to 18-24 dB across columns) are presented as direct post-silicon measurements rather than quantities derived from equations, fitted parameters, or self-citations. No load-bearing step reduces by construction to its own inputs; the work is self-contained against external benchmarks of fabricated hardware behavior.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard assumptions about circuit variation in 22-nm FDSOI and the ability of a digital processor to measure and correct analog column behavior; no new physical entities or ad-hoc constants are introduced in the abstract.

axioms (1)
  • domain assumption Analog column variations in resistive CIM can be measured and corrected by a digital control loop without significant additional error sources
    Invoked when claiming that RISC-V controlled calibration improves SNR to 18-24 dB

pith-pipeline@v0.9.0 · 5890 in / 1311 out tokens · 32733 ms · 2026-05-19T09:14:32.071297+00:00 · methodology

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Reference graph

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