Multiple double matrix multiplication on FP64 tensor cores is achieved by splitting doubles into 13-bit quarters with trailing zeros, enabling error-free inner products without branching renormalization.
Acceleration of multi-component multiple-precision arithmetic with branch-free algorithms and SIMD vectorization
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abstract
Multiple-precision floating-point branch-free algorithms can significantly accelerate multi-component arithmetic implemented by combining hardware-based binary64 and binary32, particularly for triple- and quadruple-precision computations. In this study, we achieved benchmark results on x86 and ARM CPU platforms to quantify the accelerations achieved in linear computations and polynomial evaluation by integrating these algorithms.
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Multiple Double Arithmetic on NVIDIA Tensor Cores
Multiple double matrix multiplication on FP64 tensor cores is achieved by splitting doubles into 13-bit quarters with trailing zeros, enabling error-free inner products without branching renormalization.