InCoder-32B-Thinking uses error-feedback synthesized thinking traces and a code world model to reach top open-source scores on general and industrial code benchmarks including 81.3% on LiveCodeBench and 84.0% on CAD-Coder.
VeriThoughts: Enabling automated Verilog code generation using reasoning and formal verification
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StepPRM-RTL combines stepwise process-reward modeling, RAFT, and MCTS to fine-tune LLMs for RTL code, claiming over 10% gains in functional correctness on Verilog/VHDL benchmarks.
Empirical study identifies patterns in how model classes respond to structured prompts, optimization, and other techniques across two Verilog benchmarks.
A survey of LLM applications in electronic design automation and hardware security, covering opportunities, vulnerabilities, and countermeasures.
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InCoder-32B-Thinking: Industrial Code World Model for Thinking
InCoder-32B-Thinking uses error-feedback synthesized thinking traces and a code world model to reach top open-source scores on general and industrial code benchmarks including 81.3% on LiveCodeBench and 84.0% on CAD-Coder.