LAsset applies LLMs to extract primary, secondary, and inter-module security assets from SoC and IP designs, reporting up to 93% recall while reducing expert manual effort.
LASHED: LLMs and static hardware analysis for early detection of RTL bugs
3 Pith papers cite this work. Polarity classification is still indexing.
3
Pith papers citing it
years
2026 3verdicts
UNVERDICTED 3representative citing papers
VeriCWEty applies embedding-based analysis to detect CWEs in Verilog with 89% precision on examples like CWE-1244/1245 and 96% accuracy at line level.
A survey of LLM applications in electronic design automation and hardware security, covering opportunities, vulnerabilities, and countermeasures.
citing papers explorer
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LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
LAsset applies LLMs to extract primary, secondary, and inter-module security assets from SoC and IP designs, reporting up to 93% recall while reducing expert manual effort.
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VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
VeriCWEty applies embedding-based analysis to detect CWEs in Verilog with 89% precision on examples like CWE-1244/1245 and 96% accuracy at line level.
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LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
A survey of LLM applications in electronic design automation and hardware security, covering opportunities, vulnerabilities, and countermeasures.