Disaggregating cache operators from compute and overlapping them across the two classifier-free-guidance branches turns cross-timestep caching into up to 1.80x real end-to-end speedup on edge GPUs when the cache overflows VRAM.
TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning
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abstract
Recent studies from several hyperscalars pinpoint to embedding layers as the most memory-intensive deep learning (DL) algorithm being deployed in today's datacenters. This paper addresses the memory capacity and bandwidth challenges of embedding layers and the associated tensor operations. We present our vertically integrated hardware/software co-design, which includes a custom DIMM module enhanced with near-data processing cores tailored for DL tensor operations. These custom DIMMs are populated inside a GPU-centric system interconnect as a remote memory pool, allowing GPUs to utilize for scalable memory bandwidth and capacity expansion. A prototype implementation of our proposal on real DL systems shows an average 6.2-17.6x performance improvement on state-of-the-art recommender systems.
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cs.AR 1years
2026 1verdicts
CONDITIONAL 1representative citing papers
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CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation
Disaggregating cache operators from compute and overlapping them across the two classifier-free-guidance branches turns cross-timestep caching into up to 1.80x real end-to-end speedup on edge GPUs when the cache overflows VRAM.