Pith. sign in

REVIEW 4 major objections 7 minor 83 references

CODA claims that separating compute from cache operations lets cross-timestep caching deliver up to 1.80x speedups on edge video diffusion GPUs, with energy efficiency up to 1.74x.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

T0 review · deepseek-v4-flash

2026-08-02 00:44 UTC pith:OEBKBVTA

load-bearing objection Solid co-design paper with a real problem and a clean ablation, but the 1.80x speedup rests on a composed-timeline overlap assumption that needs a real microbenchmark before it's credible. the 4 major comments →

arxiv 2607.14908 v1 pith:OEBKBVTA submitted 2026-07-16 cs.AR cs.DC

CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

Yuanpeng Zhang (Peking University) , YuXuan Wu (Peking University) , Yitong Xiao (Peking University) , Chenhao Xue (Peking University) , Yi Ren (Peking University) , Cong Li (Peking University) , Yihan Yin (Peking University) , Dimin Niu (Alibaba Group Inc.)
show 1 more author
Guangyu Sun (Peking University)
This is my paper
classification cs.AR cs.DC
keywords video diffusion modelscross-timestep cachingnear-memory processingcompute-cache operator disaggregationedge inferenceclassifier-free guidancehardware-software co-designDIMM-NMP
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

On memory-constrained edge GPUs, video diffusion models can be accelerated by cross-timestep caching, which reuses intermediate features across denoising steps. But the cache quickly overflows VRAM into host memory, and the cache operators remain interleaved with compute operators, so the reuse gains are erased by PCIe communication and serialization. CODA argues that the key is compute-cache operator disaggregation: run the memory-bound cache operators on a lightweight DIMM-side near-memory engine, reorganize them into coarse coalesced segments, and use the independence of the two Classifier-Free Guidance branches to hide cache-side execution behind the other branch's dense compute. If this holds, the cache path becomes largely free, yielding up to 1.80x end-to-end speedup and 1.74x energy efficiency with generation quality close to the state-of-the-art caching baseline.

Core claim

The central claim is that the bottleneck of cross-timestep caching on edge video diffusion is not the redundant computation but the communication and serialization overhead of the cache path once the cache overflows VRAM. The paper shows that a native near-memory offload is insufficient, because cache operators remain chain-dependent with compute operators and cause repeated PCIe round trips. CODA's compute-cache operator disaggregation—dense compute on the xPU, cache operators on a rank-level DIMM-side near-memory engine, fused into coarse segments, and overlapped across CFG branches—hides the remaining cache-path cost behind the xPU compute window. Evaluated across seven video diffusion mo

What carries the argument

Compute-cache operator disaggregation: a separation of the execution path into dense compute operators (left on the centralized xPU) and memory-bound cache operators (retrieval, residual, scale, and fusion) that run on a lightweight DIMM-side near-memory engine. Its three supporting mechanisms are the hybrid hardware-aware caching scheduler, which coalesces fragmented cache operators into coarse segments and sets boundaries via simulated annealing; the tiled operator-fusion dataflow on a 4-PE, 64KB-buffer NME; and CFG-interleaved pipelining, which unrolls the two CFG branches into separate streams so one branch's cache segment overlaps the other's dense compute.

Load-bearing premise

The speedup claims rest on the composed-timeline evaluation model that assumes independent GPU, PCIe, and NMP events overlap; if real hardware exposes serialization, the 'hidden' cache latency becomes exposed and the gains shrink.

What would settle it

Build or simulate the CODA system on real silicon/full-system with the tile-level GEMM/DMA overlap enabled and measure end-to-end latency for Open-Sora 720p; if the measured speedup is far below 1.80x and the PCIe/NMP overhead appears on the critical path, the claim that cache-path latency is largely hidden is falsified.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • If CODA is correct, cross-timestep caching becomes a practical acceleration technique on edge GPUs even when the cache cannot fit in VRAM.
  • The speedup grows with resolution, since attention compute scales superlinearly with tokens while the cache footprint scales linearly, so higher resolutions gain the most.
  • Naive near-memory offloading alone can be slower than host offloading; scheduling and overlap are necessary to convert reuse into speedup.
  • CODA's quality is close to conservative PAB and better than aggressive PAB, so the system gains do not come from more aggressive cache policies.
  • The lightweight NME adds under 0.1% area and power overhead per DIMM, making the hardware addition small relative to the reported gains.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The 1.80x figure depends on the composed-timeline model that allows independent events to overlap; a real-system implementation may expose extra serialization from kernel-launch limits or PCIe contention, so the realized speedup could be lower.
  • The CFG-overlap window is specific to models that run two independent branches with a shared fusion point; video models that drop CFG or fuse branches differently would lose the hiding mechanism.
  • The scheduler's offline profiling of 10 prompts and simulated-annealing search means a per-model one-time cost; in practice, model updates would require re-running this search, which the paper does not quantify.
  • A natural extension is diffusion language models with KV-cache reuse, but the paper notes the token-level dynamics differ and the CFG overlap opportunity may not exist, so a new overlap mechanism would be needed.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 7 minor

Summary. CODA targets video diffusion inference at the edge in the regime where cross-timestep caching (CTC) overflows GPU VRAM and spills to host memory. The paper observes that cache operators are low-arithmetic-intensity, tightly interleaved with dependent xPU compute, and, when offloaded, become PCIe- and serialization-bound. The proposed design has three pillars: (i) a hardware-aware scheduler that selects cached operator instances and coalesces them into contiguous, same-timestep segments (Eqs. (1)-(2), optimized offline by simulated annealing); (ii) a lightweight rank-level DIMM-side near-memory engine (NME) that executes these segments near host DRAM with a tiled SIMD fusion dataflow; and (iii) CFG-interleaved pipelining, which unrolls the two classifier-free-guidance branches into asynchronous streams so that one branch's cache-path execution (PCIe + NMP) overlaps the other branch's dense xPU compute, plus a dynamic runtime adjustment (DRA) safeguard. Claimed results are up to 1.80× end-to-end speedup and 1.74× energy-efficiency gain with quality close to the PAB caching baseline. These figures come from the composed evaluation of §5.1.1, which merges Nsight GPU kernel times, Ramulator 2.0 NMP cycle counts, and analytic PCIe timings under the rule that 'independent events may overlap.'

Significance. The problem is well motivated and the core framing — making the cache path explicit, coalesced, and overlapable rather than merely moving it closer to memory — is a useful systems contribution. The paper ships a coherent staged ablation (Fig. 11: naive NMP alone is neutral-to-negative; the scheduler produces the first gain; CFG pipelining produces the second), which is the right structure for a multi-mechanism claim. Creditable strengths include: measured GPU kernel times on an RTX 4090, cycle-level DRAM simulation, RTL synthesis of the NME in TSMC 7nm with a design-space exploration (Fig. 16), quality evaluation against an external CTC baseline (PAB) with VBench/PSNR/SSIM/LPIPS across seven models and multiple resolutions, and a rare-input safeguard (DRA) with its own latency accounting and a triggered-fraction bound (<7%). The rank-level NME choice is argued with an Amdahl-style analysis (§4.3.1). If the overlap assumption can be validated or bounded, the paper would make a valuable point: disaggregation plus scheduling plus CFG overlap — not NMP hardware alone — is what converts algorithmic reuse into real end-to-end speedup. The main risk is that the headline speedup is generat

major comments (4)
  1. [§4.4, §5.1.1] The headline 1.80×/1.74× results rest entirely on the §5.1.1 composed timeline: Nsight kernel times, Ramulator 2.0 NMP cycles, and analytic PCIe timings are merged under 'independent events may overlap.' No real-system measurement validates this rule, and §4.4's own wording ('Ideally, by the time...') concedes it is a design target. The entire gain attributed to CFG-Interleaved Pipelining — the difference between Fig. 11(c) and (d) — is thus assumed, not measured: the model embeds near-ideal tile-level GEMM/DMA overlap, contention-free bidirectional PCIe, and negligible launch/serialization overheads, and §4.3.1's assertion that evaluation shows PCIe/NMP overhead is hidden cites the same composed model. This is load-bearing for the central claim. Please add (i) a real-system overlap microbenchmark on the RTX 4090 (concurrent GEMM and bidirectional PCIe DMA), or (ii) a sensitivity sweep o
  2. [§4.2.1 Eq. (2); §4.4] Eq. (2) penalizes segments with T_exec(S_i) > T_optimal, and §4.4 defines T_optimal as the xPU branch compute window. The scheduler therefore rejects, by construction, any segment whose NMP+PCIe latency cannot fit inside the assumed hiding window; the 'hidden PCIe/NMP' portion in Fig. 11(d) is partly an output of the optimizer's constraint set rather than an independently demonstrated property of the hardware. This is not fatal — co-tuning scheduler and pipeline is legitimate co-design — but it prevents Fig. 11 from cleanly separating the scheduler contribution from the pipelining contribution. Report the distribution of T_exec vs T_optimal for the selected segments, and include an ablation with the T_optimal penalty weakened or removed, to show that the overlap reflects a real hardware property and not the cost function alone.
  3. [§5.2–§5.3, Table 2] The Fig. 10 comparison runs Cache-HostOffload and Cache-NaiveNMP with PAB-Cons while CODA uses its own more aggressive policy, and §5.2 asserts this is 'at a similar video-quality operating point.' Table 2 does not support that for several models: Open-Sora Plan CODA (PSNR 17.19, SSIM 0.472, LPIPS 0.497) is far from PAB-Cons (20.38, 0.670, 0.315) and close to PAB-Aggr (16.82, 0.473, 0.544); CogVideoX and Wan 2.1 also show clear degradation (Wan LPIPS 0.148 vs 0.084). Part of the measured speedup may thus reflect cache-policy aggressiveness rather than the NMP/overlap architecture. The matched-scheduler ablation (Fig. 12) is the right idea; extend it to a matched-quality comparison (equal PSNR/LPIPS to PAB-Cons) and add an ideal-VRAM variant of CODA's own policy. The abstract's 'preserving competitive generation quality' should be qualified to identify which PAB configuration is the refer
  4. [§3.1, §4.2.1, §5.1] The motivation is the VRAM-overflow regime ('a 480p, 2-second video can already exceed the VRAM of...RTX 4090'), and the NMP path exists specifically to serve a host-resident cache. But the scheduler targets only 25–50% of the full CTC cache ratio (§4.2.1), and the paper never reports the actual cache footprint or whether the evaluated workloads actually overflow 24 GB VRAM under CODA's own policy. If the selected cache plus weights and activations fits in VRAM, the relevant baseline is an ideal on-VRAM cache, and the HostOffload comparison is confounded by cache footprint rather than isolating the architecture. Report per-workload selected-cache sizes and overflow amounts for the Fig. 10 configurations, and add an unlimited-VRAM cache baseline to Figs. 11/12.
minor comments (7)
  1. [Abstract; Fig. 10] The abstract states the 1.80× speedup is 'compared with a state-of-the-art caching algorithm,' but Fig. 10 normalizes to Vanilla-GPU; the speedup over the PAB-based Cache-HostOffload baseline is roughly 1.3–1.45×. State the normalization basis explicitly in the abstract and figure captions.
  2. [§5.1.1] The text cites 'PCIe 4.0 x16 ... aggregate bidirectional bandwidth of approximately 64 GB/s.' This is the nominal bidirectional peak; achievable bandwidth is lower and direction turnarounds are not free. State whether link efficiency is modeled; this interacts with the first major comment.
  3. [Fig. 10/11] The numeric labels on the bars are extremely small and the y-axis label is duplicated in Fig. 10; improve legibility and add 'Normalized to Vanilla-GPU' directly on the y-axis.
  4. [Table 2] For the Original row, PSNR/SSIM/LPIPS are shown as '-' because they are computed against the Original itself; say so in the caption. Also state in the caption that the Fig. 10 system baselines use PAB-Cons.
  5. [§5.6] The DRA safety threshold and the fallback step count N_fb are never given numerical values. Report the values used and a brief statement on sensitivity, since they are free parameters of the design.
  6. [§4.4] The kernel-launch overhead of splitting the batch-2 CFG dispatch into two asynchronous streams is acknowledged but never quantified in the composed timeline. Include an estimate or measurement of this overhead per timestep.
  7. [References] Reference [64] appears with an odd author field ('DefTruth vipshop.com'); fix the citation formatting. Also check that all cited 2025/2026 items are accurate and public at the time of submission.

Circularity Check

0 steps flagged

No significant circularity: CODA's speedup is a model-based estimate whose overlap assumption is a validation risk, not a circular reduction.

full rationale

The paper's central derivation chain is not circular. The scheduler in Eq. (2) uses T_optimal as a design target representing the CFG branch compute window, and the evaluation in Section 5.1.1 composes independently measured GPU, PCIe, and NMP events into a dependency timeline under an explicit rule that independent events may overlap. The reported hidden PCIe/NMP overhead is a modeled consequence of that timeline rule and of the scheduler's chosen segments, not a quantity that is identical to an input by construction. The overlap rule is a modeling assumption that could be challenged on real hardware, but that is a correctness/validation concern, not a definitional equivalence. There is no load-bearing self-citation: the only same-author citations (e.g., SpecPIM [32], GNNear [77]) appear as background NMP examples and do not support CODA's core speedup or quality claims. The speedup and quality are evaluated against external baselines (Vanilla-GPU, Cache-HostOffload, Cache-NaiveNMP, PAB), and the quality results are independent of the scheduler's cost model. Thus no circular step is exhibited.

Axiom & Free-Parameter Ledger

6 free parameters · 5 axioms · 1 invented entities

The system half of the claim rests on the CTC similarity premise (imported from prior work), the composed-timeline evaluation model, the accuracy of Ramulator-modeled NMP behavior, and the scheduler's own cost model (Eqs. 1–2) with hand-set weights and T_optimal. The quality half is grounded externally (VBench, PSNR, SSIM, LPIPS). The 1.80x magnitude is therefore determined largely by the paper's own models and chosen parameters.

free parameters (6)
  • Scheduler objective weights = w_cost=3, w_frag=0.8, w_dev=1
    Hand-chosen in §4.2.1; no sensitivity analysis reported. These weights determine which operators are cached and the coalesced segment structure that drives the speedup claim.
  • Per-model target cache ratio = 25%–50%
    Sets the ceiling on compute savings and therefore on achievable speedup; chosen by the authors per model, not derived from any optimality criterion.
  • T_optimal masking window = xPU branch compute window (not numerically tabulated)
    Eq. (2) penalizes segments whose NMP latency exceeds this window; the reported 'hidden' PCIe/NMP time is fit to this target, making the overlap gain partly self-fulfilling.
  • DRA safety threshold and fallback width N_fb = not specified
    'Predefined safety threshold' in §4.2.2 controls the <7% DRA trigger rate and its cost, but no value is given.
  • NME hardware configuration = 4 PEs x 8 lanes, 64 KB buffer, 1 GHz
    Chosen via the DSE in Fig. 16 at the saturation point; all NMP latency, area, and energy numbers depend on this configuration.
  • GEMM macro-tiling granularity = not specified
    §4.4's tile-level DMA overlap relies on subGEMM boundaries being exposed with acceptable launch overhead; the granularity is never stated.
axioms (5)
  • domain assumption Cross-timestep feature similarity is high enough that replacing selected operators with cached features preserves generation quality
    Borrowed from the CTC literature (FORA, PAB); used in §2.2 and by the scheduler's similarity-based cacheability signal.
  • domain assumption The composed event timeline (dependent events serialized, independent events overlapped) faithfully predicts end-to-end latency
    §5.1.1: the entire speedup measurement is built on this composition rule plus Nsight, Ramulator, and analytic PCIe timings.
  • domain assumption Ramulator 2.0's DDR4 timing model captures NMP multi-stream access behavior, including conflict-aware placement effects
    §5.1.1 and §4.3.3; NMP cycle counts are the input to the composed timeline, and concurrent cache-tile accesses are modeled only in simulation.
  • domain assumption Rank-level NMP bandwidth is sufficient; tiled fusion is <20% of cache-path latency for segment lengths n=2/3/4
    §4.3.1 argues near-bank PIM would add little end-to-end benefit; this is an estimate used to justify the architectural choice, not a hardware measurement.
  • domain assumption GPU GEMM macro-tiling exposes subGEMM boundaries without kernel-launch overhead that offsets the overlap gains
    §4.4 depends on asynchronous per-tile dispatch and event synchronization being practically realizable on an NVIDIA GPU.
invented entities (1)
  • DIMM-side Near-Memory Engine (NME) with rank-level center-buffer organization no independent evidence
    purpose: Executes memory-bound cache operators (residual/scale/gated fusion) and the L1 shadow-monitoring datapath near DRAM
    The entire speedup rests on this new hardware block's assumed bandwidth, latency, and power; the only evidence is in-paper RTL synthesis and Ramulator modeling, with no real-system measurement or external falsifiable handle.

pith-pipeline@v1.3.0-alltime-deepseek · 27202 in / 19656 out tokens · 169517 ms · 2026-08-02T00:44:04.274080+00:00 · methodology

0 comments
read the original abstract

Deploying Video Diffusion Models (VDMs) on edge devices is appealing for localized and privacy-preserving generation, but their iterative Transformer-based denoising remains too slow for practical local inference. Cross-Timestep Caching (CTC) has emerged as a promising direction for reducing redundant computation, reusing activations across adjacent denoising steps rather than modifying model weights, while largely preserving generation fidelity. However, on memory-constrained edge GPUs, CTC requires a massive cache footprint that quickly exceeds on-device VRAM and forces the cache into host memory. More fundamentally, cache operators remain tightly interleaved and chain-dependent with native compute operators, so naive near-memory offloading still incurs repeated PCIe exchanges for residual and fusion computations, turning cache reuse into a communication- and serialization-bound execution flow. We therefore propose CODA, an algorithm-hardware co-designed architecture centered on Compute-Cache Operator Disaggregation. CODA separates dense compute paths and memory-bound cache paths across the xPU and a lightweight DIMM-side near-memory engine, reorganizes fragmented cache activity into hardware-friendly coalesced segments, and exploits Classifier-Free Guidance (CFG) branch independence to overlap xPU compute with cache-side execution. Experiments show that CODA achieves up to 1.80x end-to-end speedup and 1.74x higher energy efficiency, while preserving competitive generation quality compared with a state-of-the-art caching algorithm.

Figures

Figures reproduced from arXiv: 2607.14908 by Chenhao Xue (Peking University), Cong Li (Peking University), Dimin Niu (Alibaba Group Inc.), Guangyu Sun (Peking University), Yihan Yin (Peking University), Yi Ren (Peking University), Yitong Xiao (Peking University), Yuanpeng Zhang (Peking University), YuXuan Wu (Peking University).

Figure 1
Figure 1. Figure 1: Motivation and solution overview. (a) Host memory cache offloading can erase expected CTC gains on edge devices, [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: DiT blocks of VDMs (left). Cross-Timestep Caching, [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Motivation and insight. (a) Cache storage quickly exceeds edge-GPU VRAM as video size grows. (b) With host-offloaded [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: CODA overview and cross-stack synergy. while memory-bound cache operators are assigned to the Light￾weight DIMM-NMP. Importantly, this near-memory subsystem is intentionally streamlined for the low-arithmetic-intensity access and fusion patterns of cache operators, providing a low-overhead execution substrate for the disaggregated cache path. Building on this separation and mapping, CFG-Interleaved Pipelin… view at source ↗
Figure 5
Figure 5. Figure 5: CODA execution walkthrough. Coalesced segments [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Spatial-temporal heterogeneity of cacheability: (a) [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: CODA architecture: (a) Compute-cache operator disaggregation between the xPU and DIMM-NMP subsystem. (b) [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) DIMM-aligned partitioning of the input activa [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: CODA execution evolution: (a) Scheduler-only flow, [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: CODA speedup and energy efficiency improvement on different models normalized to Vanilla-GPU. [PITH_FULL_IMAGE:figures/full_fig_p010_10.png] view at source ↗
Figure 12
Figure 12. Figure 12: Ablation study with same CODA caching policy: [PITH_FULL_IMAGE:figures/full_fig_p011_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: GPU dense-compute utilization across timesteps [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗
Figure 16
Figure 16. Figure 16: Architecture DSE for NMP buffer and PE numbers. [PITH_FULL_IMAGE:figures/full_fig_p012_16.png] view at source ↗
Figure 15
Figure 15. Figure 15: Latency breakdown at the triggered timestep when [PITH_FULL_IMAGE:figures/full_fig_p012_15.png] view at source ↗

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

83 extracted references · 11 canonical work pages · 7 internal anchors

  1. [1]

    Young, Frank Liu, and Jeffrey S

    Kazi Asifuzzaman, Narasinga Rao Miniskar, Aaron R. Young, Frank Liu, and Jeffrey S. Vetter. 2023. A survey on processing-in-memory techniques: Advances and challenges.Memories - Materials, Devices, Circuits and Systems4 (July 2023), 100022. https://doi.org/10.1016/j.memori.2022.100022

    arXiv 2023

  2. [2]

    Gulcin Baykal, Halil Faruk Karagoz, Taha Binhuraib, and Gozde Unal. 2023. ProtoDiffusion: Classifier-Free Diffusion Guidance with Prototype Learning. https://doi.org/10.48550/arXiv.2307.01924 arXiv:2307.01924 [cs]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.2307.01924 2023

  3. [3]

    Philipp Becker, Abhinav Mehrotra, Ruchika Chavhan, Malcolm Chadwick, Luca Morreale, Mehdi Noroozi, Alberto Gil Ramos, and Sourav Bhattacharya. 2025. EDiT: Efficient Diffusion Transformers with Linear Compressed Attention. https: //doi.org/10.48550/arXiv.2503.16726 arXiv:2503.16726 [cs]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.2503.16726 2025

  4. [4]

    Tiwei Bie, Maosong Cao, Kun Chen, Lun Du, Mingliang Gong, Zhuochen Gong, Yanmei Gu, Jiaqi Hu, Zenan Huang, Zhenzhong Lan, Chengxi Li, Chongxuan Li, Jianguo Li, Zehuan Li, Huabin Liu, Lin Liu, Guoshan Lu, Xiaocheng Lu, Yuxin Ma, Jianfeng Tan, Lanning Wei, Ji-Rong Wen, Yipeng Xing, Xiaolu Zhang, Junbo Zhao, Da Zheng, Jun Zhou, Junlin Zhou, Zhanchao Zhou, Li...

    Pith/arXiv arXiv 2025

  5. [5]

    Andreas Blattmann, Tim Dockhorn, Sumith Kulal, Daniel Mendelevitch, Maciej Kilian, Dominik Lorenz, Yam Levi, Zion English, Vikram Voleti, Adam Letts, Varun Jampani, and Robin Rombach. 2023. Stable Video Diffusion: Scaling Latent Video Diffusion Models to Large Datasets. https://doi.org/10.48550/arXiv.2311.15127 arXiv:2311.15127 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2311.15127 2023

  6. [6]

    Arwen Bradley and Preetum Nakkiran. 2024. Classifier-Free Guidance is a Predictor-Corrector. https://doi.org/10.48550/arXiv.2408.09000 arXiv:2408.09000 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2408.09000 2024

  7. [7]

    Xinhua Chen, Sitao Huang, Cong Guo, Chiyue Wei, Yintao He, Jianyi Zhang, Hai Helen Li, and Yiran Chen. 2026. DPad: Efficient Diffusion Language Models with Suffix Dropout. InThe Fourteenth International Conference on Learning Representations. https://openreview.net/forum?id=0yOsSMU1eY

    2026

  8. [8]

    Shuang Cheng, Yihan Bian, Dawei Liu, Linfeng Zhang, Qian Yao, Zhongbo Tian, Wenhai Wang, Qipeng Guo, Kai Chen, Biqing Qi, and Bowen Zhou. 2025. SDAR: A Synergistic Diffusion-AutoRegression Paradigm for Scalable Sequence Generation. arXiv:2510.06303 [cs.LG] https://arxiv.org/abs/2510.06303

    arXiv 2025

  9. [9]

    Huanpeng Chu, Wei Wu, Chengjie Zang, and Kun Yuan. 2024. QNCD: Quantiza- tion Noise Correction for Diffusion Models. https://doi.org/10.48550/arXiv.2403. 19140 arXiv:2403.19140 [cs]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.2403 2024

  10. [10]

    Hyungjin Chung, Jeongsol Kim, Geon Yeong Park, Hyelin Nam, and Jong Chul Ye. 2025. CFG++: Manifold-constrained Classifier Free Guidance for Diffusion Models. InThe Thirteenth International Conference on Learning Representations. https://openreview.net/forum?id=E77uvbOTtp

    2025

  11. [11]

    Hanshuai Cui, Zhiqing Tang, Zhifei Xu, Zhi Yao, Wenyi Zeng, and Weijia Jia

  12. [12]

    Hangliang Ding, Dacheng Li, Runlong Su, Peiyuan Zhang, Zhijie Deng, Ion Stoica, and Hao Zhang. 2025. Efficient-vDiT: Efficient Video Diffusion Transformers With Attention Tile. arXiv:2502.06155 [cs.CV] https://arxiv.org/abs/2502.06155

    Pith/arXiv arXiv 2025

  13. [13]

    Li Ding, Jun Liu, Shan Huang, and Guohao Dai. 2025. ViDA: Video Diffusion Trans- former Acceleration with Differential Approximation and Adaptive Dataflow. InProceedings of the 30th Asia and South Pacific Design Automation Conference (Tokyo, Japan)(ASPDAC ’25). Association for Computing Machinery, New York, NY, USA, 148–154. https://doi.org/10.1145/365861...

    arXiv 2025

  14. [14]

    Weichen Fan, Chenyang Si, Junhao Song, Zhenyu Yang, Yinan He, Long Zhuo, Ziqi Huang, Ziyue Dong, Jingwen He, Dongwei Pan, Yi Wang, Yuming Jiang, Yaohui Wang, Peng Gao, Xinyuan Chen, Hengjie Li, Dahua Lin, Yu Qiao, and Ziwei Liu. 2025. Vchitect-2.0: Parallel Transformer for Scaling Up Video Diffusion Models. https://doi.org/10.48550/arXiv.2501.08453 arXiv:...

    Pith/arXiv arXiv doi:10.48550/arxiv.2501.08453 2025

  15. [15]

    Zhentao Fan, Zongzuo Wang, and Weiwei Zhang. 2025. TaoCache: Structure- Maintained Video Generation Acceleration. https://doi.org/10.48550/arXiv.2508. 08978 arXiv:2508.08978 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2508 2025

  16. [16]

    Alibaba Cloud Group. 2026. Wan AI: Leading AI Video Generation Model. https: //wan.video/

    2026

  17. [18]

    Oliveira, and Onur Mutlu

    Juan Gómez-Luna, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F. Oliveira, and Onur Mutlu. 2022. Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture. https://doi.org/10.48550/ arXiv.2105.03814 arXiv:2105.03814 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2105.03814 2022

  18. [19]

    Yefei He, Jing Liu, Weijia Wu, Hong Zhou, and Bohan Zhuang. 2024. EfficientDM: Efficient Quantization-Aware Fine-Tuning of Low-Bit Diffusion Models. InThe Twelfth International Conference on Learning Representations. https://openreview. net/forum?id=UmMa3UNDAz 13 MICRO 2026, October 31–November 04, 2026, Athens, Greece Yuanpeng Zhang et al

    2024

  19. [20]

    Jonathan Ho and Tim Salimans. 2022. Classifier-Free Diffusion Guidance. https: //doi.org/10.48550/arXiv.2207.12598 arXiv:2207.12598 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2207.12598 2022

  20. [21]

    Ziqi Huang, Yinan He, Jiashuo Yu, Fan Zhang, Chenyang Si, Yuming Jiang, Yuanhan Zhang, Tianxing Wu, Qingyang Jin, Nattapol Chanpaisit, Yaohui Wang, Xinyuan Chen, Limin Wang, Dahua Lin, Yu Qiao, and Ziwei Liu. 2023. VBench: Comprehensive Benchmark Suite for Video Generative Models. https://doi.org/ 10.48550/arXiv.2311.17982 arXiv:2311.17982 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2311.17982 2023

  21. [22]

    Wenqin Huangfu, Xueqi Li, Shuangchen Li, Xing Hu, Peng Gu, and Yuan Xie

  22. [23]

    Yuchu Jiang, Yue Cai, Xiangzhong Luo, Jiale Fu, Jiarui Wang, Chonghan Liu, and Xu Yang. 2026. d$^2$Cache: Accelerating Diffusion-Based LLMs via Dual Adaptive Caching. InThe Fourteenth International Conference on Learning Repre- sentations. https://openreview.net/forum?id=SjInfpK5RM

    2026

  23. [24]

    Sunitha Kanipakam, Vishnupriya S Devarajulu, and Tulasi Kavarakuntla. 2025. Privacy-Preserving AI Inference in Edge Systems: Ethical and Architectural Trade- offs. In2025 IEEE International Performance, Computing, and Communications Conference (IPCCC). 1–6. https://doi.org/10.1109/IPCCC66453.2025.11304649 ISSN: 2374-9628

    arXiv 2025

  24. [25]

    Lee, Meng Li, Bert Maher, Dheevatsa Mudigere, Maxim Naumov, Martin Schatz, Mikhail Smelyanskiy, Xiaodong Wang, Brandon Reagen, Carole-Jean Wu, Mark Hempstead, and Xuan Zhang

    Liu Ke, Udit Gupta, Benjamin Youngjae Cho, David Brooks, Vikas Chandra, Utku Diril, Amin Firoozshahian, Kim Hazelwood, Bill Jia, Hsien-Hsin S. Lee, Meng Li, Bert Maher, Dheevatsa Mudigere, Maxim Naumov, Martin Schatz, Mikhail Smelyanskiy, Xiaodong Wang, Brandon Reagen, Carole-Jean Wu, Mark Hempstead, and Xuan Zhang. 2020. RecNMP: Accelerating Personalized...

    arXiv 2020

  25. [26]

    Donghyuk Kim, Jae-Young Kim, Wontak Han, Jongsoon Won, Haerang Choi, Yongkee Kwon, and Joo-Young Kim. 2025. Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics. 13, 3 (2025), 739–752. https://doi.org/10.1109/TETC.2024.3493132 arXiv:2305.13970 [eess]

    arXiv 2025

  26. [27]

    Weijie Kong, Qi Tian, Zijian Zhang, Rox Min, Zuozhuo Dai, Jin Zhou, Jiangfeng Xiong, Xin Li, Bo Wu, Jianwei Zhang, Kathrina Wu, Qin Lin, Junkun Yuan, Yanxin Long, Aladdin Wang, Andong Wang, Changlin Li, Duojun Huang, Fang Yang, Hao Tan, Hongmei Wang, Jacob Song, Jiawang Bai, Jianbing Wu, Jinbao Xue, Joey Wang, Kai Wang, Mengyang Liu, Pengyu Li, Shuai Li, ...

    Pith/arXiv arXiv 2025

  27. [28]

    Youngeun Kwon, Yunjae Lee, and Minsoo Rhu. 2019. TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning. https://doi.org/10.48550/arXiv.1908.03072 arXiv:1908.03072 [cs]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.1908.03072 2019

  28. [29]

    ByteDance AI Lab. 2026. Seedance 2.0: The Next Generation of AI Video. https: //fal.ai/seedance-2.0

    2026

  29. [30]

    Donghun Lee, Jinin So, MINSEON AHN, Jong-Geon Lee, Jungmin Kim, Jeonghyeon Cho, Rebholz Oliver, Vishnu Charan Thummala, Ravi shankar JV, Sachin Suresh Upadhya, Mohammed Ibrahim Khan, and Jin Hyun Kim. 2022. Im- proving In-Memory Database Operations with Acceleration DIMM (AxDIMM). In Proceedings of the 18th International Workshop on Data Management on New...

    arXiv 2022

  30. [31]

    Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyudong Hwang, Jeongje Park, Kyeongpil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Donguc Ko, Younggun Jun, Keewon Cho, Ilwoong Kim, Choungki Song, Chunseok Jeon...

    arXiv 2022

  31. [32]

    Cong Li, Zhe Zhou, Size Zheng, Jiaxi Zhang, Yun Liang, and Guangyu Sun

  32. [33]

    En Li, Liekang Zeng, Zhi Zhou, and Xu Chen. 2020. Edge AI: On-Demand Accelerating Deep Neural Network Inference via Edge Computing.IEEE Transactions on Wireless Communications19, 1 (Jan. 2020), 447–457. https: //doi.org/10.1109/TWC.2019.2946140

    arXiv 2020

  33. [34]

    Huize Li, Dan Chen, and Tulika Mitra. 2025. SADIMM: Accelerating Sparse Attention Using DIMM-Based Near-Memory Processing .IEEE Trans. Comput. 74, 02 (Feb. 2025), 542–554. https://doi.org/10.1109/TC.2024.3500362

    arXiv 2025

  34. [35]

    Wenhao Li, Daohai Yu, Gen Luo, Yuxin Zhang, Fei Chao, Rongrong Ji, Yifan Wu, Jiaxin Liu, Ziyang Gong, and Zimu Liao. 2026. Out of the Memory Barrier: A Highly Memory Efficient Training System for LLMs with Million-Token Contexts. https://doi.org/10.48550/arXiv.2602.02108 arXiv:2602.02108 [cs] version: 2

    work page doi:10.48550/arxiv.2602.02108 2026

  35. [36]

    2025.Towards Understanding the Mechanisms of Classifier-Free Guidance

    Xiang Li, Rongrong Wang, and Qing Qu. 2025.Towards Understanding the Mechanisms of Classifier-Free Guidance. https://arxiv.org/abs/2505.19210v3

    arXiv 2025

  36. [37]

    Yanxi Li and Chengbin Du. 2025. Optimizing Quantized Diffusion Models via Distillation with Cross-Timestep Error Correction.Proceedings of the AAAI Conference on Artificial Intelligence39, 17 (April 2025), 18530–18538. https: //doi.org/10.1609/aaai.v39i17.34039

    work page doi:10.1609/aaai.v39i17.34039 2025

  37. [38]

    Yiwei Li, Yuxin Jin, Boyu Tian, Huanchen Zhang, and Mingyu Gao. [n. d.]. ANS- MET: Approximate Nearest Neighbor Search with Near-Memory Processing and Hybrid Early Termination. InProceedings of the 52nd Annual International Symposium on Computer Architecture(New York, NY, USA, 2025-06-20)(ISCA ’25). Association for Computing Machinery, 1093–1107. https://...

    arXiv 2025

  38. [39]

    Bin Lin, Yunyang Ge, Xinhua Cheng, Zongjian Li, Bin Zhu, Shaodong Wang, Xianyi He, Yang Ye, Shenghai Yuan, Liuhan Chen, et al. 2024. Open-Sora Plan: Open-Source Large Video Generation Model.arXiv preprint arXiv:2412.00131 (2024)

    Pith/arXiv arXiv 2024

  39. [40]

    Dong Liu, Yanxuan Yu, Jiayi Zhang, Yifan Li, Ben Lengerich, and Ying Nian Wu

  40. [41]

    Jiacheng Liu, Peiliang Cai, Qinming Zhou, Yuqi Lin, Deyang Kong, Benhao Huang, Yupei Pan, Haowen Xu, Chang Zou, Junshu Tang, Shikang Zheng, and Linfeng Zhang. 2025. FreqCa: Accelerating Diffusion Models via Frequency- Aware Caching. https://doi.org/10.48550/arXiv.2510.08669 arXiv:2510.08669 [cs] version: 1

    doi:10.48550/arxiv.2510.08669 2025

  41. [42]

    Jun Liu, Shulin Zeng, Li Ding, Widyadewi Soedarmadji, Hao Zhou, Zehao Wang, Jinhao Li, Jintao Li, Yadong Dai, Kairui Wen, Shan He, Yaqi Sun, Yu Wang, and Guohao Dai. 2025. FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs. InProceedings of the 2025 ACM/SIGDA International Symposium on Field Prog...

    arXiv 2025

  42. [43]

    Jiacheng Liu, Chang Zou, Yuanhuiyi Lyu, Junjie Chen, and Linfeng Zhang. 2025. From Reusing to Forecasting: Accelerating Diffusion Models with TaylorSeers. https://doi.org/10.48550/arXiv.2503.06923 arXiv:2503.06923 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2503.06923 2025

  43. [44]

    https://doi.org/10.48550/arXiv.2505.20353 arXiv:2505.20353 [cs] version: 3

    FastCache: Fast Caching for Diffusion Transformer Through Learnable Lin- ear Approximation. https://doi.org/10.48550/arXiv.2505.20353 arXiv:2505.20353 [cs] version: 3

    doi:10.48550/arxiv.2505.20353

  44. [45]

    Liu Liu, Jilan Lin, Zheng Qu, Yufei Ding, and Yuan Xie. 2021. ENMC: Extreme Near-Memory Classification via Approximate Screening. InMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture(New York, NY, USA, 2021-10-17)(MICRO ’21). Association for Computing Machinery, 1309–1322. https://doi.org/10.1145/3466752.3480090

    arXiv 2021

  45. [46]

    Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xi- aowei Li, Yinhe Han, and Ying Wang. 2025. Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. In2025 IEEE Interna- tional Symposium on High Performance Computer Architecture (HPCA)(2025-03). 1751–1765. https://doi.org/10.1109/HPCA61900.2025.00129

    arXiv 2025

  46. [47]

    Nisa Bostancı, Ataberk Olgun, A

    Haocong Luo, Yahya Can Tuğrul, F. Nisa Bostancı, Ataberk Olgun, A. Giray Yağlıkçı, and Onur Mutlu. 2024. Ramulator 2.0: A Modern, Modular, and Ex- tensible DRAM Simulator.IEEE Comput. Archit. Lett.23, 1 (Jan. 2024), 112–116. https://doi.org/10.1109/LCA.2023.3333759

    arXiv 2024

  47. [48]

    Jiacheng Liu, Chang Zou, Yuanhuiyi Lyu, Fei Ren, Shaobo Wang, Kaixin Li, and Linfeng Zhang. 2025. SpeCa: Accelerating Diffusion Transformers with Specula- tive Feature Caching. InProceedings of the 33rd ACM International Conference on Multimedia(2025-10-27). 10024–10033. https://doi.org/10.1145/3746027.3755331 arXiv:2509.11628 [cs]

    arXiv 2025

  48. [49]

    Xin Ma, Yaohui Wang, Xinyuan Chen, Gengyun Jia, Ziwei Liu, Yuan-Fang Li, Cunjian Chen, and Yu Qiao. 2025. Latte: Latent Diffusion Transformer for Video Generation.Transactions on Machine Learning Research(2025)

    2025

  49. [50]

    Xinyin Ma, Runpeng Yu, Gongfan Fang, and Xinchao Wang. 2025. dKV-Cache: The Cache for Diffusion Language Models. InThe Thirty-ninth Annual Conference on Neural Information Processing Systems. https://openreview.net/forum?id= Gppo2JImHs

    2025

  50. [51]

    Mustafa Rafique, Franck Cappello, and Bogdan Nicolae

    Avinash Kumar Maurya, M. Mustafa Rafique, Franck Cappello, and Bogdan Nicolae. 2025. MLP-Offload: Multi-Level, Multi-Path Offloading for LLM Pre- training to Break the GPU Memory Wall. InProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (New York, NY, USA, 2025-11-15)(SC ’25). Association for Comp...

    arXiv 2025

  51. [52]

    Xuran Ma, Yexin Liu, Yaofu Liu, Xianfeng Wu, Mingzhe Zheng, Zihao Wang, Ser- Nam Lim, and Harry Yang. 2025. Model Reveals What to Cache: Profiling-Based Feature Reuse for Video Diffusion Models. (October 2025), 17150–17159

    2025

  52. [53]

    Meta-Learning via Classifier(-free) Diffusion Guidance

    Elvis Nava, Seijin Kobayashi, Yifei Yin, Robert K. Katzschmann, and Benjamin F. Grewe. 2023. Meta-Learning via Classifier(-free) Diffusion Guidance. https: //doi.org/10.48550/arXiv.2210.08942 arXiv:2210.08942 [cs]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.2210.08942 2023

  53. [54]

    Shen Nie, Fengqi Zhu, Zebin You, Xiaolu Zhang, Jingyang Ou, Jun Hu, JUN ZHOU, Yankai Lin, Ji-Rong Wen, and Chongxuan Li. 2025. Large Language Diffusion Models. InThe Thirty-ninth Annual Conference on Neural Information Processing Systems. https://openreview.net/forum?id=KnqiC0znVF

    2025

  54. [55]

    OpenAI. 2026. Sora 2: Video Generation Models as World Simulators. https: //openai.com/index/sora-2/

    2026

  55. [56]

    P. J. Meaney, L. D. Curley, G. D. Gilda, M. R. Hodges, D. J. Buerkle, R. D. Siegl, and R. K. Dong. 2015. The IBM z13 memory subsystem for big data.IBM Journal of Research and Development59, 4/5 (2015), 4:1–4:11. https://doi.org/10.1147/JRD. 2015.2429031

    arXiv 2015

  56. [57]

    William Peebles and Saining Xie. 2023. Scalable Diffusion Models with Trans- formers. arXiv:2212.09748 [cs.CV] https://arxiv.org/abs/2212.09748

    Pith/arXiv arXiv 2023

  57. [58]

    Prin Phunyaphibarn, Phillip Y Lee, Jaihoon Kim, and Minhyuk Sung. 2025. Un- conditional Priors Matter! Improving Conditional Generation of Fine-Tuned Diffusion Models. (2025)

    2025

  58. [59]

    Lucas Relic, Roberto Azevedo, Yang Zhang, Markus Gross, and Christopher Schroers. 2025. Bridging the Gap between Gaussian Diffusion Models and Uni- versal Quantization for Image Compression. https://doi.org/10.48550/arXiv.2504. 02579 arXiv:2504.02579 [eess]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.2504 2025

  59. [60]

    Jaehyun Park, Jaewan Choi, Kwanhee Kyung, Michael Jaemin Kim, Yongsuk Kwon, Nam Sung Kim, and Jung Ho Ahn. 2024. AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference. InProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2 (ASPLOS ’24,...

    arXiv 2024

  60. [61]

    Pratheba Selvaraju, Tianyu Ding, Tianyi Chen, Ilya Zharkov, and Luming Liang

  61. [62]

    VideoSys Team. 2024. VideoSys: An Easy and Efficient System for Video Genera- tion. https://github.com/NUS-HPC-AI-Lab/VideoSys

    2024

  62. [63]

    1987.Simulated annealing

    Peter JM Van Laarhoven, Emile HL Aarts, Peter JM van Laarhoven, and Emile HL Aarts. 1987.Simulated annealing. Springer

    1987

  63. [64]

    Shreshth Saini, Shashank Gupta, and Alan Bovik. 2025. Rectified CFG++ for Flow Based Models. InThe Thirty-ninth Annual Conference on Neural Information Processing Systems. https://openreview.net/forum?id=NosdT1FHPv

    2025

  64. [65]

    Team Wan, Ang Wang, Baole Ai, Bin Wen, Chaojie Mao, Chen-Wei Xie, Di Chen, Feiwu Yu, Haiming Zhao, Jianxiao Yang, Jianyuan Zeng, Jiayu Wang, Jingfeng Zhang, Jingren Zhou, Jinkai Wang, Jixuan Chen, Kai Zhu, Kang Zhao, Keyu Yan, Lianghua Huang, Mengyang Feng, Ningyi Zhang, Pandeng Li, Pingyu Wu, Ruihang Chu, Ruili Feng, Shiwei Zhang, Siyang Sun, Tao Fang, T...

    Pith/arXiv arXiv doi:10.48550/arxiv.2503.20314 2025

  65. [66]

    https: //doi.org/10.48550/arXiv.2407.01425 arXiv:2407.01425 [cs]

    FORA: Fast-Forward Caching in Diffusion Transformer Acceleration. https: //doi.org/10.48550/arXiv.2407.01425 arXiv:2407.01425 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2407.01425

  66. [67]

    Zihao Wu. 2025. InvarDiff: Cross-Scale Invariance Caching for Accelerated Diffusion Models. https://doi.org/10.48550/arXiv.2512.05134 arXiv:2512.05134 [cs]

    work page doi:10.48550/arxiv.2512.05134 2025

  67. [68]

    Haocheng Xi, Shuo Yang, Yilong Zhao, Chenfeng Xu, Muyang Li, Xiuyu Li, Yujun Lin, Han Cai, Jintao Zhang, Dacheng Li, et al. 2025. Sparse VideoGen: Accelerating Video Diffusion Transformers with Spatial-Temporal Sparsity.International Conference on Machine Learning(2025)

    2025

  68. [69]

    DefTruth vipshop.com. 2025. Cache-DiT: A PyTorch-native Inference Engine with Hybrid Cache Acceleration and Massive Parallelism for DiTs. https: //github.com/vipshop/cache-dit.git

    2025

  69. [70]

    Zhuoyi Yang, Jiayan Teng, Wendi Zheng, Ming Ding, Shiyu Huang, Jiazheng Xu, Yuanming Yang, Wenyi Hong, Xiaohan Zhang, Guanyu Feng, Da Yin, Yuxuan Zhang, Weihan Wang, Yean Cheng, Bin Xu, Xiaotao Gu, Yuxiao Dong, and Jie Tang. 2025. CogVideoX: Text-to-Video Diffusion Models with An Expert Transformer. https://doi.org/10.48550/arXiv.2408.06072 arXiv:2408.06072 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2408.06072 2025

  70. [71]

    Chengyue Wu, Hao Zhang, Shuchen Xue, Zhijian Liu, Shizhe Diao, Ligeng Zhu, Ping Luo, Song Han, and Enze Xie. 2026. Fast-dLLM: Training-free Acceleration of Diffusion LLM by Enabling KV Cache and Parallel Decoding. InThe Fourteenth International Conference on Learning Representations. https://openreview.net/ forum?id=3Z3Is6hnOT

    2026

  71. [72]

    Dingkun Zhang, Sijia Li, Chen Chen, Qingsong Xie, and Haonan Lu. 2025. LAPTOP-Diff: Layer Pruning and Normalized Distillation for Compressing Diffu- sion Models. arXiv:2404.11098 [cs.CV] https://arxiv.org/abs/2404.11098

    Pith/arXiv arXiv 2025

  72. [73]

    Xuanlei Zhao, Xiaolong Jin, Kai Wang, and Yang You. 2025. Real-Time Video Generation with Pyramid Attention Broadcast. InThe Thirteenth International Conference on Learning Representations. https://openreview.net/forum?id= hDBrQ4DApF

    2025

  73. [74]

    Zhen Xing, Qijun Feng, Haoran Chen, Qi Dai, Han Hu, Hang Xu, Zuxuan Wu, and Yu-Gang Jiang. 2024. A Survey on Video Diffusion Models. https://doi.org/ 10.48550/arXiv.2310.10647 arXiv:2310.10647 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2310.10647 2024

  74. [75]

    Dongqi Zheng. 2025. Diffusion Models on the Edge: Challenges, Optimizations, and Applications. https://doi.org/10.48550/arXiv.2504.15298 arXiv:2504.15298 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2504.15298 2025

  75. [76]

    Yuzhe Yao, Feng Tian, Jun Chen, Haonan Lin, Guang Dai, Yong Liu, and Jingdong Wang. 2024. Timestep-Aware Correction for Quantized Diffusion Models. https: //doi.org/10.48550/arXiv.2407.03917 arXiv:2407.03917 [cs]

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.48550/arxiv.2407.03917 2024

  76. [77]

    Zhe Zhou, Cong Li, Xuechao Wei, Xiaoyang Wang, and Guangyu Sun. 2023. GNNear: Accelerating Full-Batch Training of Graph Neural Networks with near- Memory Processing. InProceedings of the International Conference on Parallel Architectures and Compilation Techniques(New York, NY, USA, 2023-01-27)(PACT ’22). Association for Computing Machinery, 54–68. https:...

    arXiv 2023

  77. [78]

    Chang Zou, Xuyang Liu, Ting Liu, Siteng Huang, and Linfeng Zhang

  78. [79]

    Yang Zhao, Yanwu Xu, Zhisheng Xiao, Haolin Jia, and Tingbo Hou. 2024. Mo- bileDiffusion: Instant Text-to-Image Generation on Mobile Devices. InComputer Vision – ECCV 2024: 18th European Conference, Milan, Italy, September 29–October 4, 2024, Proceedings, Part LXII(Milan, Italy). Springer-Verlag, Berlin, Heidelberg, 225–242. https://doi.org/10.1007/978-3-0...

    work page doi:10.1007/978-3-031-73033-7_13 2024

  79. [81]

    Zangwei Zheng, Xiangyu Peng, Tianji Yang, Chenhui Shen, Shenggui Li, Hongxin Liu, Yukun Zhou, Tianyi Li, and Yang You. 2024. Open-Sora: Democratizing Efficient Video Production for All. https://doi.org/10.48550/arXiv.2412.20404 arXiv:2412.20404 [cs]

    Pith/arXiv arXiv doi:10.48550/arxiv.2412.20404 2024

  80. [2019]

    InProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture(New York, NY, USA, 2019-10-12)(MICRO-52)

    MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm. InProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture(New York, NY, USA, 2019-10-12)(MICRO-52). Association for Computing Machinery, 587–599. https://doi.org/10.1145/3352460. 3358329

    doi:10.1145/3352460 2019

Showing first 80 references.