Chopim lets a host CPU and near-memory accelerators share DRAM concurrently through bank partitioning, NDA write throttling, and an interleaving-compatible data layout, giving up to 2x faster SVRG training in simulation.
Application-transparent near-memory processing architecture with memory channel network,
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Near Data Acceleration with Concurrent Host Access
Chopim lets a host CPU and near-memory accelerators share DRAM concurrently through bank partitioning, NDA write throttling, and an interleaving-compatible data layout, giving up to 2x faster SVRG training in simulation.