An integrated multi-level methodology is presented to reduce memory interferences and improve predictability in high-performance multi-core systems for safety-critical applications.
ARM Cortex-A72 MPCore Pro- cessor Technical Reference Manual –r0p3, Decem- ber 2016
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Interferences within a certifiable design methodology for high-performance multi-core platforms
An integrated multi-level methodology is presented to reduce memory interferences and improve predictability in high-performance multi-core systems for safety-critical applications.