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arxiv: 2604.09559 · v1 · submitted 2026-02-11 · 💻 cs.DC · cs.OS· cs.SE

Interferences within a certifiable design methodology for high-performance multi-core platforms

Mohamed Amine Khelassi (LECA) , Felix Suchert (TU Dresden) , Abderaouf Amalou (Nantes Univ - ECN , LS2N) , Benjamin Lesage , Anika Christmann , Robin Hapka , Jeronimo Castrillon (TU Dresden)
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Mihail Asavoae (LECA) Mathieu Jan (LECA) Claire Pagetti Selma Saidi
This is my paper

Pith reviewed 2026-05-16 02:58 UTC · model grok-4.3

classification 💻 cs.DC cs.OScs.SE
keywords levelexecutioninterferenceinterferencesmulti-corereducesystemabstraction
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The pith

An integrated multi-level methodology is presented to reduce memory interferences and improve predictability in high-performance multi-core systems for safety-critical applications.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

High-performance computers with many cores are powerful but hard to use in planes and cars because programs can interfere with each other through shared memory, making it hard to predict how long tasks will take. This paper outlines a way to tackle this by using tools at four levels: a formal model of the hardware to find interference paths, machine learning to spot problematic code sections, compiler changes to alter how memory is accessed, and rules in the operating system to keep interfering tasks apart. By combining these, the approach aims to make execution more predictable so the systems can be certified as safe for critical uses.

Core claim

We present a methodology that brings together several tools that operate at different abstraction levels to reduce memory interference and improve the system's predictability, thereby easing the certification process of multi-core systems in safety-critical domains.

Load-bearing premise

That the tools at different levels (PHYLOG formal model, ML code analysis, MLIR transformations, Linux cgroups) can be effectively integrated without conflicts and that their combined application will measurably reduce interferences and enable certification.

Figures

Figures reproduced from arXiv: 2604.09559 by Abderaouf Amalou (Nantes Univ - ECN, Anika Christmann, Benjamin Lesage, Claire Pagetti, Felix Suchert (TU Dresden), Jeronimo Castrillon (TU Dresden), LS2N), Mathieu Jan (LECA), Mihail Asavoae (LECA), Mohamed Amine Khelassi (LECA), Robin Hapka, Selma Saidi.

Figure 1
Figure 1. Figure 1: Overview of the interference-aware design method [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Sensitivity of L2 Accesses to Variations in Matrix [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Overview of the PML model for the Raspberry Pi 4 Board [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Prediction accuracy when varying parameter [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 4
Figure 4. Figure 4: Final-layer attention matrices without (top) and with [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 7
Figure 7. Figure 7: Job-wise execution times for matrix1. The dashed line represents the 30ms deadline [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Cumulative Distribution Function (CDF) of execu [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Deadline Miss Ratio comparison. cution scenario, τvictim meets all deadlines as expected. Un￾der Interference execution, approximately 50% of jobs miss their deadline. This ratio is consistent with the period rela￾tionship: τvictim (T = 100 ms) and τnoise (T = 200 ms) overlap on every second job of τvictim, causing contention in￾duced slowdown precisely when both tasks execute concur￾rently. Such a miss ra… view at source ↗
read the original abstract

The adoption of high-performance multi-core platforms in avionics and automotive systems introduces significant challenges in ensuring predictable execution, primarily due to shared resource interferences. Many existing approaches study interference from a single angle-for example, through hardware-level analysis or by monitoring software execution. However, no single abstraction level is sufficient on its own. Hardware behavior, program structure, and system configuration all interact, and a complete view is needed to understand where interferences come from and how to reduce them. In this paper, we present a methodology that brings together several tools that operate at different abstraction levels. At the lowest level, PHYLOG provides a formal model of the hardware and identifies possible interference channels using micro-architectural transactions. At the program level, machine learning analysis locates the exact parts of the code that are most sensitive to shared-resource contention. At the compilation level, MLIR-based transformations use this information to reshape memory access patterns and reduce pressure on shared resources. Finally, at the system level, Linux cgroups enforce static execution constraints to prevent highly interfering tasks from running together. The goal of our approach is to reduce memory interference and improve the system's predictability, thereby easing the certification process of multi-core systems in safety-critical domains.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper is a descriptive proposal of a multi-level methodology integrating PHYLOG hardware modeling, ML-based code analysis, MLIR transformations, and Linux cgroups to reduce memory interference in multi-core platforms. No equations, derivations, fitted parameters, predictions, or self-referential reductions appear anywhere in the text. All steps are conceptual descriptions of tool integration rather than results derived from the paper's own outputs. No load-bearing self-citations, ansatzes, or uniqueness claims reduce the central claim to its inputs by construction. The work is self-contained as a methodology outline without circular logic.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The work is a high-level methodology proposal; the abstract contains no explicit free parameters, mathematical axioms, or newly postulated entities.

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Reference graph

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