Maps differentiable logic-gate networks to CMOS silicon via netlist conversion and area-minimizing loss, with first simulated 130nm hard-macro achieving 97% MNIST accuracy at 41.8M inferences/sec and 83.88mW.
IEEE Journal of Solid-State Circuits , volume =
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Silicon Aware Neural Networks
Maps differentiable logic-gate networks to CMOS silicon via netlist conversion and area-minimizing loss, with first simulated 130nm hard-macro achieving 97% MNIST accuracy at 41.8M inferences/sec and 83.88mW.