A protocol maps arbitrary linear transformations to coin and step operators of a quantum walk, then to experimental settings in a time-multiplexed hybrid photonic platform, with claims of scalability and resilience to imperfections.
Demonstration of a quantum C-NOT Gate in a Time-Multiplexed fully reconfigurable photonic processor
3 Pith papers cite this work. Polarity classification is still indexing.
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abstract
The two-qubit controlled-not (C-NOT) gate is an essential component for gate-based quantum circuits. In fact, its operation, combined with single qubit rotations allows to realise any quantum circuit. Several strategies have been adopted in order to build quantum gates. Among them, photonics offers the dual advantage of excellent isolation from the environment and ease of manipulation at the single qubit level. Here we adopt a scalable time-multiplexed approach in order to build a fully reconfigurable architecture capable of implementing a post-selected C-NOT gate with a fidelity of $(93.8 \pm 1.4)\%$. We then show how our time-multiplexed platform can be employed to combine a C-NOT and a single qubit gate in order to generate the four Bell states.
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UNVERDICTED 3representative citing papers
A synthetic time-domain photonic processor achieves exponential hardware reduction for universal linear transformations and exceeds cluster-state quantum computation thresholds in benchmarks on boosted Bell state measurements.
Experimental demonstration of a post-selected C-NOT gate with (93.8 ± 1.4)% fidelity in a time-multiplexed fully reconfigurable photonic processor, extended to Bell state generation.
citing papers explorer
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Resource-efficient universal photonic processor based on time-multiplexed hybrid architectures
A protocol maps arbitrary linear transformations to coin and step operators of a quantum walk, then to experimental settings in a time-multiplexed hybrid photonic platform, with claims of scalability and resilience to imperfections.
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Hardware-Efficient Universal Linear Transformations for Optical Modes in the Synthetic Time Dimension
A synthetic time-domain photonic processor achieves exponential hardware reduction for universal linear transformations and exceeds cluster-state quantum computation thresholds in benchmarks on boosted Bell state measurements.
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Demonstration of a quantum C-NOT Gate in a Time-Multiplexed fully reconfigurable photonic processor
Experimental demonstration of a post-selected C-NOT gate with (93.8 ± 1.4)% fidelity in a time-multiplexed fully reconfigurable photonic processor, extended to Bell state generation.