A proposed vector-processor memory hierarchy with an ultra-wide register and data shufflers improves compute-to-memory ratio and processing-element utilization for low-reuse CNNs like MobileNet.
Title resolution pending
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2025 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
Addressing memory bandwidth scalability in vector processors for streaming applications
A proposed vector-processor memory hierarchy with an ultra-wide register and data shufflers improves compute-to-memory ratio and processing-element utilization for low-reuse CNNs like MobileNet.