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REVIEW 4 major objections 5 minor 1 cited by

Addressing memory bandwidth scalability in vector processors for streaming applications

T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Wide, shallow on-chip memory scales bandwidth linearly with cores

desk verdict Provet's linear-bandwidth memory hierarchy is a genuinely interesting architecture template, but the headline 9.4x/24.7x gains rest on an uncontrolled comparison that needs rework before the claims are citeable. read the letter →

arxiv 2505.12856 v1 pith:QX34TZBY submitted 2025-05-19 cs.AR

Jordi Altayo , Paul Delestrac , David Novo , Simey Yang , Debjyoti Bhattacharjee , Francky Catthoor This is my paper · ORCID
classification cs.AR
keywords memorybandwidthvectorprocessorsystolicarrayverywideregisterdatareuseCNNacceleratorultra-wideSRAMshuffler
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to show that memory-bandwidth throttling in data-parallel AI/ML accelerators is not an inevitable cost of scaling: reshaping the on-chip memory hierarchy can remove it. It proposes Provet, a vector-processor extension whose global memory is an ultra-wide, shallow SRAM feeding a single-word very-wide register (VWR) with asymmetric ports, plus two shufflers. The claim is that this arrangement gives memory bandwidth that grows linearly with the number of processing elements, whereas systolic arrays grow only with the square root, so utilization no longer depends on heavy data reuse. A curious reader cares because modern networks such as MobileNet contain depth-wise convolutions with little reuse, and the paper reports that those are exactly where current accelerators collapse and Provet gains the most.

What carries the argument

The load-bearing object is the very wide register (VWR): a single-row, one-word-deep buffer with an asymmetric interface, one port matching the ultra-wide SRAM width and the other matching the narrower SIMD/VFU width, so every wide read is amortized over many compute cycles. Around it the paper places an ultra-wide shallow SRAM as the global on-chip memory (width typically 8 times the SIMD width, depth 1-32 words), a coarse tile shuffler that moves VWR-sized blocks between SRAM and VWR, and a fine VFU shuffler that slides single operands inside a SIMD word. The mechanism that carries the argument is the width ratio N: the VWR's asymmetry guarantees an N-fold reduction in SRAM accesses independently of application reuse, and the wide-shallow SRAM keeps the energy per bit low because the access cost depends on depth rather than width.

What would settle it

Build the VWR and its two asymmetric ports in a 28 nm RTL-to-layout flow and measure area, cycle time, and per-access energy against a conventional vector register file of equal total storage; if the VWR's per-access energy is not far below the SRAM's, or if its access time exceeds the cycle budget used in the latency model, the reported utilization and compute-to-memory advantages would need to be recomputed downward.

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Extended reading notes

Core claim

On the paper's own terms, the central discovery is a scaling law: put a very wide, one-word-deep register between an ultra-wide SRAM and the SIMD lanes, give that register different port widths on the two sides, and the memory system's bandwidth becomes proportional to the number of processing elements instead of to their square root. Because the VWR is a single word, it needs no address decoding or multi-port register-file multiplexing; because its memory-side port is N times wider than its SIMD-side port, one SRAM access is consumed over N compute cycles. The authors map convolution and fully connected layers onto this structure using a tile shuffler for coarse movement and a VFU shuffler for fine, one-operand sliding, and they report that a shuffle distance of one is enough for those kernels. In their comparisons, Provet keeps high PE utilization across ResNet, AlexNet, and MobileNet layers, with the largest margins where data reuse is lowest: up to 9.43x utilization and 24.67x compute-to-memory ratio over Eyeriss for the MobileNet 7x7 layer.

Load-bearing premise

The whole gain story assumes that a single-word, ultra-wide VWR with asymmetric ports and no address decoding can be built with negligible area, delay, and energy overhead relative to a conventional vector register file; the paper presents an SRAM energy model and a shuffler layout comparison, but not a full physical implementation of the VWR itself.

Editorial extensions

If this is right

  • Peak bandwidth in this design scales as $\sim \alpha N$ with processing-element count, so adding PEs does not push the memory system into throttling the way the $\sim\sqrt{N}$ scaling of systolic arrays does.
  • For networks with depth-wise separable convolutions and other low-reuse layers, MobileNet being the paper's running example, PE utilization and compute-to-memory ratio stay high; the reported improvements over Eyeriss reach 9.43x and 24.67x on the MobileNet 7x7 layer.
  • Because the same shuffle distance of one covers CONV and fully-connected kernels, the flexible interconnect can be a small specialized shuffler rather than a full crossbar; the paper's post-layout comparison puts the shuffler at roughly 7x less area and 5x fewer gates.
  • Size mismatches between the array width and image width are absorbed by partitioning the image or packing two images side by side, with the duplicated border region from convolution sliding kept below 5% for 11x11 kernels.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The linear-bandwidth argument is architectural; the physical cost of the VWR itself is not yet demonstrated. A natural extension is an RTL implementation of the VWR and its asymmetric ports; if per-access energy or delay there is not small relative to the SRAM access it replaces, the gain estimates shrink.
  • The same wide-shallow-plus-asymmetric-buffer recipe could be applied outside CNNs to any streaming data-parallel workload with low reuse, such as signal processing, sparse inference, or batched small matrices, since the mechanism is about access amortization rather than about convolution specifically.
  • The reported results depend on hand-mapped Provet kernels and on the chosen baselines' mapping tools; the mixed numbers, for example 0.94x utilization vs Eyeriss on an AlexNet 13x13 layer, suggest that the architecture's advantage is mapping-sensitive and would benefit from an automated mapping compiler before broad claims are drawn.
  • A testable design rule falls out of the shuffle-distance-1 result: profile an application suite for shuffle range, then fix the shuffler's maximum distance at the smallest range that covers the kernels, trading a little flexibility for wire length and energy.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes a vector processor extension called Provet that combines a 1D PE organization with a three-level on-chip memory hierarchy: an ultra-wide shallow SRAM, a very wide single-word register (VWR) with asymmetric ports, and two granularities of data shufflers (tile-level and VFU-level). The authors argue that this organization makes available memory bandwidth scale linearly with the number of PEs, in contrast to 2D systolic arrays whose boundary-fed bandwidth scales as the square root of PE count. They describe mappings of CNN layers (ResNet, AlexNet, MobileNet) and report large utilization and compute-to-memory-ratio improvements over Eyeriss, TPU, ARA, and an NVIDIA A100 GPU, with the largest gains for low-reuse MobileNet layers. The paper explicitly defers detailed energy analysis and several implementation-level issues, such as the physical design of the VWR and the loop-buffer control structure.

Significance. If the central claim holds, the paper addresses a real bottleneck in low-reuse, streaming data-parallel workloads and offers a concrete architectural template that is conceptually distinct from both edge-fed systolic arrays and conventional vector register files. The structural argument for linear bandwidth scaling is plausible and clearly explained, and the CACTI SRAM study and post-layout shuffler comparison are useful first-order data points. However, the quantitative evidence is not yet convincing: the Provet mappings are hand-crafted, the baselines come from heterogeneous tools and methodologies, the GPU stall correction is internally inconsistent, and no code, mapping listings, or data are released. Because the paper's headline results in Table 3 are the main support for the bandwidth-scalability claim, these evaluation issues are load-bearing. The manuscript also contains several explicitly deferred items (VWR physical implementation, loop-buffer details, energy analysis) that prevent the architecture's practical advantages from being assessed. These problems are substantial but fixable with a more transparent and controlled evaluation.

major comments (4)
  1. [Section 7, Table 3, Eq. (3)] The headline quantitative claim is not a controlled comparison. Provet utilization is derived from manual mappings following the methodology in Section 6, while Eyeriss and TPU results are generated with the ZigZag DSE framework and ARA and GPU results come from the original authors' code and cuDNN, respectively. Because utilization is defined as U = Lmin/Lreal (Eq. 3), a manually chosen Lreal for Provet has a direct and potentially large influence on the result, and the paper provides no mapping listing, sensitivity analysis, or released code to show that the Provet numbers are representative. The caption of Table 3 also states that red values are preliminary estimations, but it does not identify which entries are affected. This asymmetry is load-bearing because Table 3 is the main evidence behind the reported up-to-9.43x utilization and up-to-24.67x compute-to-memory-ratio improvements.
  2. [Section 7, Fig. 11b] The GPU utilization correction is internally inconsistent. The text states that control stalls are 75.6% of total stalls and that GPU utilization is scaled up by this factor, citing Fig. 11b, but Fig. 11b reports 75.64% for memory, 15.73% for control, and 8.62% for others. The claimed control fraction of 75.6% is incompatible with the figure's control share of 15.73%. Additionally, correcting only the GPU for control stalls while the other architecture models are assumed not to include control overhead requires an explicit justification that those architectures incur comparable control overhead; otherwise the GPU comparison is biased. Please resolve the inconsistency and provide the underlying cycle counts and the exact correction formula.
  3. [Section 5.1, Fig. 5a] The central bandwidth-scaling claim is not directly demonstrated. Fig. 5a plots schematic 'linear' and 'sqrt' scaling curves, and the text argues from the VWR's asymmetric interface that bandwidth grows linearly with PE count, but no experiment or analytical model measures Provet's available bandwidth or utilization as a function of the number of VFUs. The scaling factors alpha and beta in Fig. 5a are not defined or derived, and Table 3 is only an indirect and, as noted above, uncontrolled proxy. A direct scaling study that varies the number of VFUs and SRAM width, or at least a formal parameterized model with stated assumptions, is needed to support the claim that Provet avoids the square-root bandwidth wall.
  4. [Sections 4.1, 4.3.4, and 1.1] The paper explicitly defers key implementation supports for its main architectural element. No RTL or physical implementation of the VWR and its asymmetric interface is provided; the evidence is limited to a CACTI SRAM study and a post-layout comparison of the shuffler against a crossbar (Table 1). Section 1.1 also states that a detailed energy-efficiency analysis is left for future work. Since the architecture's benefit is predicated on the VWR having small area, delay, and energy overhead relative to a conventional register file, these missing pieces weaken the practical significance of the claimed bandwidth and compute-to-memory improvements. Please provide at least a synthesis-level evaluation of the VWR, or explicitly state which conclusions are conditional on unverified overhead assumptions.
minor comments (5)
  1. [Sections 4.3.2, 4.3.4, and 7] Several unresolved cross-references remain: 'explained in ??' in Section 4.3.2, 'concept explained in ??' in Section 4.3.4, and 'section ??' in Section 7. These must be resolved before publication.
  2. [Table 3] The caption says red values are preliminary estimations, but no entries in the table are visibly marked red; please specify which rows or columns are preliminary or remove the statement.
  3. [Throughout] There are numerous typographical and terminology inconsistencies, including 'assymetry' for 'asymmetry', 'file-grained' for 'fine-grained', 'suffle' for 'shuffle', 'implemente' for 'implement', 'Proved' for 'Provet', 'DPU' used interchangeably with 'VFU', 'NVIDIA Coorporation', and '2046 bit' (likely '2048 bit') in Section 6.2.1.
  4. [Section 6.1] The pseudo-code uses the instruction 'GLV', which does not appear in the instruction list in Table 2 (the closest listed instruction is 'GLMV'), and the variable i is reused for both the input-row count and the kernel-pixel index, making the mapping example harder to follow.
  5. [Table 4 and Figure 9] The GPU results appear to be for batch size 1, but this is not stated in the text; please state the batch size explicitly and explain why the A100 reads and latency values in Table 4 are so high relative to the other architectures.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation chain: the headline bandwidth and utilization/CMR claims are measured from architectural properties and mapping simulations, not fitted to their own outputs.

full rationale

The paper's central results are not circular. The linear-bandwidth claim (Section 5.1) is an architectural property of the proposed 1D organization with an ultra-wide SRAM/VWR whose width is tied to the number of VFUs; it is stated as a design characteristic, not derived from an independent first-principles calculation that would need to be checked for circularity. The utilization and compute-to-memory-ratio numbers in Section 7 (Table 3, Figures 9-10) are computed from Eq. (3), U = Lmin/Lreal, and Eq. (4), CMR = Ncompute/Nmemory, where Lmin is obtained by summing MAC operations and dividing by PE count, Lreal is read from the mapping's cycle count, and Ncompute/Nmemory are instruction counts in the mappings. No fitted parameter is renamed as a prediction, and no equation is equated to its own input by construction. The self-citations in the evaluation (Delestrac et al. [11] for GPU metric extraction, and the stall-based GPU utilization correction) are external prior methodology used to calibrate the baseline, not a load-bearing theorem that forces the Provet result. The main threats to these numbers are evaluation-validity issues rather than circularity: Provet mappings are hand-written while Eyeriss/TPU mappings come from ZigZag, Table 3's caption flags red entries as preliminary without identifying them, and the text's 75.6% stall factor (calling it control) conflicts with Fig. 11b (75.64% memory, 15.73% control). These are correctness and rigor concerns, not a circular derivation.

Assumptions & free parameters 3 free parameters · 4 assumptions · 4 invented entities

The central claims rest on assumptions about SRAM energy modeling, representativeness of baseline mappings, and technology scaling, none of which are validated by measurements. The architecture introduces new components (VWR, two shufflers, loop buffers) without silicon proof. Free parameters include the VWR width ratio and the GPU stall-correction factor.

free parameters (3)
  • GPU control-stall correction factor = 75.6% (text) vs 15.73% or 75.64% (Figure 11b), inconsistent
    Used to scale GPU utilization for fair comparison; the paper's values are inconsistent between text and figure, and it is derived from one profiling run.
  • SRAM-to-SIMD width ratio = 8x (stated in Section 4.3.1)
    Design choice underpinning the VWR access asymmetry; no sensitivity analysis is provided.
  • Shuffler range and granularity = e.g., block size 512 bits, step 512 bits for tile shuffler; shuffle distance 1 for CONV
    Set by application profiling, not by an automated search; affects interconnect area, energy, and mapping flexibility.
assumptions (4)
  • domain assumption SRAM energy per word access is modeled as W*D*BL + W*WL (Equation 1), i.e., bitline and wordline capacitances dominate.
    Underlies the claim that ultra-wide shallow memory has low access energy; not validated by silicon measurements.
  • domain assumption CACTI simulation accurately estimates SRAM energy and bandwidth for the proposed ultra-wide memory.
    The energy-efficiency argument for wide-shallow SRAM rests entirely on CACTI results (Figure 2b).
  • domain assumption ZigZag-generated mappings for Eyeriss/TPU and ARA code snippets are representative of near-best achievable performance.
    The comparison's validity depends on baselines not being under-optimized relative to the hand-crafted Provet mappings.
  • domain assumption Technology scaling via DeepScaleTool to 28nm and 200 MHz is valid across heterogeneous architectures.
    Table 4 uses scaled values without validating the scaling model for each architecture class.
invented entities (4)
  • Very Wide Register (VWR)
    purpose: Single-row buffer between ultra-wide SRAM and SIMD units, providing asymmetric port widths and reducing SRAM accesses.
    No RTL implementation or silicon area/energy data are provided for the VWR itself.
  • Tile shuffler
    purpose: Coarse-grained shuffler between SRAM and VWR to allow SIMD units to access non-aligned data blocks.
    Post-layout area comparison is provided (Table 1), but no cycle-accurate model or silicon validation.
  • VFU shuffler
    purpose: Fine-grained shuffler between VWR and vector functional units to support sliding-window operations like convolution.
    Described conceptually; no independent implementation or measurement.
  • Loop buffers
    purpose: Distributed control elements that replace a centralized controller and reduce active control wire length.
    The paper explicitly defers loop buffer implementation details to future work (Section 4.4).

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Cite this review

Pith. "Pith review of Addressing memory bandwidth scalability in vector processors for streaming applications." pith.science (2026). https://pith.science/paper/QX34TZBY

@misc{pith2026250512856,
  author       = {Pith},
  title        = {Pith review of: Addressing memory bandwidth scalability in vector processors for streaming applications},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QX34TZBY}},
  note         = {Machine review of arXiv:2505.12856}
}
read the original abstract

As the size of artificial intelligence and machine learning (AI/ML) models and datasets grows, the memory bandwidth becomes a critical bottleneck. The paper presents a novel extended memory hierarchy that addresses some major memory bandwidth challenges in data-parallel AI/ML applications. While data-parallel architectures like GPUs and neural network accelerators have improved power performance compared to traditional CPUs, they can still be significantly bottlenecked by their memory bandwidth, especially when the data reuse in the loop kernels is limited. Systolic arrays (SAs) and GPUs attempt to mitigate the memory bandwidth bottleneck but can still become memory bandwidth throttled when the amount of data reuse is not sufficient to confine data access mostly to the local memories near to the processing. To mitigate this, the proposed architecture introduces three levels of on-chip memory -- local, intermediate, and global -- with an ultra-wide register and data-shufflers to improve versatility and adaptivity to varying data-parallel applications. The paper explains the innovations at a conceptual level and presents a detailed description of the architecture innovations. We also map a representative data-parallel application, like a convolutional neural network (CNN), to the proposed architecture and quantify the benefits vis-a-vis GPUs and repersentative accelerators based on systolic arrays and vector processors.

Figures

Figures reproduced from arXiv: 2505.12856 by the authors.

Figure 1
Figure 1. Comparison of the memory hierarchies. The numbered white arrows show the possible paths data can take in the architecture [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Simplified SRAM memory structure and energy cost estimations. [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Memory hierarchy and interconnect of two implementation variants of the proposed architecture. [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: Proposed architecture overview. The ultra-wide elements (4096 bits) and the SIMD unit (512 bits) are not drawn to scale to [PITH_FULL_IMAGE:figures/full_fig_p009_4.png]
Figure 5
Figure 5. Figure 5: Comparison between Provet and an ideal systolic array [PITH_FULL_IMAGE:figures/full_fig_p012_5.png]
Figure 6
Figure 6. Figure 6: Example of a convolution layer register file in GPUs is completely different from the VWR in Provet. Regarding their sizes, the GPU register file is closer to the global memory of Provet, while conceptually closer to the VWR. The mismatches in both functionality (asymm…
Figure 7
Figure 7. Figure 7: Fitting 2 kernels in 1 VFU example shows how the two images, when combined, fit exactly into the width of the VWRs. This is, however not the general case and some empty portions will often be left unfilled. These empty slots will lead to an under-utilization in the VFU…
Figure 8
Figure 8. Figure 8: Fiting 1 input map wider than the VFU For TPU and Eyeriss, mappings are generated using the ZigZag design space exploration framework, along with the hardware and mapping templates provided for those architectures to align with their respective publications [7, 15]. Th…
Figure 9
Figure 9. Figure 9: PE utilization for different layers of state-of-the-art CNNs. [PITH_FULL_IMAGE:figures/full_fig_p018_9.png]
Figure 10
Figure 10. Figure 10: Compute-to-memory access ratio for different layers of state-of-the-art CNNs. [PITH_FULL_IMAGE:figures/full_fig_p020_10.png]

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Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes

    cs.AR 2025-08 unverdicted novelty 4.0 of 10

    This design study claims its machine-learning processor cuts normalized wire length by over 2x and raises density by over 3x versus the VWR2A baseline on the IMEC A10 node.

Reference graph

Works this paper leans on

27 extracted references · 11 canonical work pages · cited by 1 Pith paper

  1. [1]

    John Backus. 2007. Can programming be liberated from the von Neumann style? a functional style and its algebra of programs . Association for Computing Machinery, New York, NY, USA, 1977. https://doi.org/10.1145/1283920.1283933

    arXiv 2007

  2. [2]

    Amirali Boroumand, Saugata Ghose, Berkin Akin, Ravi Narayanaswami, Geraldo F Oliveira, Xiaoyu Ma, Eric Shiu, and Onur Mutlu. 2021. Google neural network models for edge devices: Analyzing and mitigating machine learning inference bottlenecks. In 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 159–172

    work page 2021

  3. [3]

    Amirali Boroumand, Saugata Ghose, Berkin Akin, Ravi Narayanaswami, Geraldo F Oliveira, Xiaoyu Ma, Eric Shiu, and Onur Mutlu. 2021. Mitigating edge machine learning inference bottlenecks: An empirical study on accelerating Google edge models. arXiv preprint arXiv:2103.00768 (2021)

    arXiv 2021

  4. [4]

    Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, and Onur Mutlu. 2018. Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks. InProceedings of the Twenty-Third International Conference on Architectural Support for Progra...

    arXiv 2018

  5. [5]

    Tianshi Chen, Zidong Du, Ninghui Sun, Jia Wang, Chengyong Wu, Yunji Chen, and Olivier Temam. 2014. Diannao: A small-footprint high-throughput accelerator for ubiquitous machine-learning. ACM SIGARCH Computer Architecture News 42, 1 (2014), 269–284

    work page 2014

  6. [6]

    Yu-Hsin Chen, Joel Emer, and Vivienne Sze. 2016. Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. SIGARCH Comput. Archit. News 44, 3 (jun 2016), 367–379. doi:10.1145/3007787.3001177

    arXiv 2016

  7. [7]

    Yu-Hsin Chen, Joel Emer, and Vivienne Sze. 2016. Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. In Proceedings of the 43rd International Symposium on Computer Architecture (Seoul, Republic of Korea) (ISCA ’16). IEEE Press, 367–379. doi:10.1109/ISCA.2016.40

    doi:10.1109/isca.2016.40 2016

  8. [8]

    NVIDIA Corporation. 2023. NVIDIA CUDA Basic Linear Algebra Subroutines (cuBLAS) Library . NVIDIA Corporation. Version 11.x or higher

    work page 2023

Show all 27 references
  1. [9]

    Vidushi Dadu, Jian Weng, Sihao Liu, and Tony Nowatzki. 2019. Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (Columbus, OH, USA) (MICRO ’52). Association fo...

    2019

  2. [10]

    Paul Delestrac, Debjyoti Battacharjee, Simei Yang, Diksha Moolchandani, Francky Catthoor, Lionel Torres, and David Novo. 2024. Multi-level Analysis of GPU Utilization in ML Training Workloads. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) . IEEE, 1–6

    2024

  3. [11]

    Paul Delestrac, Jonathan Miquel, Debjyoti Bhattacharjee, Diksha Moolchandani, Francky Catthoor, Lionel Torres, and David Novo. 2024. Analyzing GPU Energy Consumption in Data Movement and Storage. In Proceedings of the 35th IEEE Conference on Application-specific Systems, Archi...

    2024

  4. [12]

    Gunnels, Greg M

    John A. Gunnels, Greg M. Henry, and Robert A. van de Geijn. 2001. A Family of High-Performance Matrix Multiplication Algorithms. InComputational Science — ICCS 2001 , Vassil N. Alexandrov, Jack J. Dongarra, Benjoe A. Juliano, René S. Renner, and C. J. Kenneth Tan (Eds.). Sprin...

    2001

  5. [13]

    Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, and Hartwig Adam

    Andrew G. Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, and Hartwig Adam

  6. [14]

    Jouppi, Andrew B

    Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, and Vaishnav Srinivas. 2012. CACTI-IO: CACTI with off-chip power-area-timing models. In 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) . 294–301

    2012

  7. [15]

    Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazi...

    2017

  8. [16]

    Svilen Kanev, Juan Pablo Darago, Kim Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, and David Brooks. 2015. Profiling a warehouse-scale computer. In Proceedings of the 42nd annual international symposium on computer architecture . 158–169

    2015

  9. [17]

    Youngeun Kwon and Minsoo Rhu. 2018. Beyond the memory wall: A case for memory-centric hpc system for deep learning. In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) . IEEE, 148–161

    2018

  10. [18]

    Linyan Mei, Pouya Houshmand, Vikram Jain, Sebastian Giraldo, and Marian Verhelst. 2021. ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Comput. 70, 8 (2021), 1160–1174. doi:10.1109/TC.2021.3059962

    2021

  11. [19]

    March 2020

    NVIDIA Coorporation. March 2020. White paper: NVIDIA AMPERE GA102 GPU architecture . Technical Report. https://www.nvidia.com/content/ PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf

    2020

  12. [20]

    Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W

    Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, and Joel Emer. 2019. Timeloop: A Systematic Approach to DNN Accelerator Evaluation. In2019 IEEE International Sympo...

    2019

  13. [21]

    Matteo Perotti, Matheus Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, and Luca Benini. 2022. A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. In 2022 IEEE 33rd International Conference on Application-specific Sys...

    2022

  14. [22]

    Satyabrata Sarangi and Bevan Baas. 2021. DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) . 1–5. doi:10.1109/ISCAS51556.2021.9401196

    2021

  15. [23]

    Pablo Villalobos, Jaime Sevilla, Lennart Heim, Tamay Besiroglu, Marius Hobbhahn, and Anson Ho. 2022. Will we run out of data? an analysis of the limits of scaling datasets in machine learning. arXiv preprint arXiv:2211.04325 1 (2022)

    2022 arXiv

  16. [24]

    Shimeng Yu, Hongwu Jiang, Shanshi Huang, Xiaochen Peng, and Anni Lu. 2021. Compute-in-memory chips for deep learning: Recent trends and prospects. IEEE circuits and systems magazine 21, 3 (2021), 31–56. Manuscript submitted to ACM Addressing memory bandwidth scalability in vec...

    2021

  17. [25]

    Jiyuan Zhang, Franz Franchetti, and Tze Meng Low. 2018. High Performance Zero-Memory Overhead Direct Convolutions. arXiv:1809.10170 [cs.LG] https://arxiv.org/abs/1809.10170

    2018 arXiv

  18. [26]

    Yangjie Zhou, Mengtian Yang, Cong Guo, Jingwen Leng, Yun Liang, Quan Chen, Minyi Guo, and Yuhao Zhu. 2021. Characterizing and Demystifying the Implicit Convolution Algorithm on Commercial Matrix-Multiplication Accelerators. In 2021 IEEE International Symposium on Workload Char...

    2021

  19. [2017]

    CoRR abs/1704.04861 (2017)

    MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications. CoRR abs/1704.04861 (2017). arXiv:1704.04861 http://arxiv.org/abs/1704.04861

    2017 arXiv

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