ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade

We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors to detect charged particles, with the goal to achieve a time resolution of 40 - 50 ps per hit, and 30 - 40 ps per track with hits from two detector layers. The ETROC1 is composed of a 5 x 5 pixel array and peripheral circuits. The pixel array includes a 4 x 4 active pixel array with an H-tree shaped network delivering clock and charge injection signals. Each active pixel is composed of various components, including a bump pad, a charge injection circuit, a pre-amplifier, a discriminator, a digital-to-analog converter, and a time-to-digital converter. These components play essential roles as the front-end link in processing LGAD signals and measuring timing-related information. The peripheral circuits provide clock signals and readout functionalities. The size of the ETROC1 chip is 7 mm x 9 mm. ETROC1 has been fabricated in a 65 nm CMOS process, and extensively tested under stimuli of charge injection, infrared laser, and proton beam. The time resolution of bump-bonded ETROC1 + LGAD chipsets reaches 42 - 46 ps per hit in the beam test.