A two-stage time-stretching TDC with discrete components

Yanbo Chu; Zhicai Zhang

REVIEW 5 major objections 5 minor 9 references

A two-stage time-stretching TDC with discrete components

T0 review · 5 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Two-stage time-stretching TDC built from discrete parts reaches 63 ps resolution using a 100 MHz clock.

desk verdict A clean prototype of a two-stage time-stretching TDC with believable but scope-relative 60–100 ps resolution; worth peer review. read the letter →

arxiv 2505.07514 v2 pith:BCVQQMFG submitted 2025-05-12 physics.ins-det hep-exnucl-ex

Yanbo Chu , Zhicai Zhang This is my paper · ORCID

classification physics.ins-dethep-exnucl-ex

keywords time-to-digitalconvertertimestretchingtwo-stageTDCdiscretecomponentsFPGAcalibrationtimingdetectors

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper establishes that a two-stage time-stretching time-to-digital converter (TDC) is a practical route to sub-100 ps timing without a fast clock or a high-speed ADC. The prototype, built from capacitors, transistors, comparators, and a low-cost FPGA, measures 10–20 ns input widths with 60–100 ps resolution at a 100 MHz clock rate, and its dead time stays below 300 ns for a 10 ns range. If the result holds, the architecture offers a low-power, low-cost readout for particle-physics timing detectors and a starting point for an ASIC aimed at future 4D pixel detectors.

What carries the argument

The load-bearing element is the time-stretching unit: a capacitor is discharged quickly while the input pulse is high and recharged slowly afterward, so the output pulse width is the input width times about $1 + I_2/I_1 \approx 11$. The TDC stretches the input pulse by a first-stage factor $S_0 \approx 10$, counts whole clock cycles $N_0$ at 100 MHz, then uses edge-detection circuits to capture the two sub-clock residuals and stretches each by another factor near 10 before counting $N_1$ and $N_2$. Reconstruction follows the formula $(N_0 T + N_1 T/S_1 + T - N_2 T/S_2)/S_0$ with $T=10$ ns, giving an effective LSB near $T/S^2 \approx 100$ ps. The two-stage arrangement keeps dead time near $T_0 S_0 + T_1 S_1$ instead of $T_0 S_0 S_1$.

What would settle it

Re-measure the 10 ns input pulse after changing the board temperature by about 10 °C or shifting the LT3092 supply voltage by a few percent without re-running the calibration; if the reconstructed width no longer matches the oscilloscope reference to within the claimed 60–100 ps, the bench-calibration assumption fails.

Watch

Extended reading notes

Core claim

The paper claims that a two-stage time-stretching TDC built from discrete components can reach sub-100 ps resolution using only a 100 MHz counter. The measured resolution is 63 ps for 10 ns input pulses and 60–100 ps over the 10–20 ns operating range, matching the predicted 67 ps obtained by combining the counter LSB, first-stage jitter, second-stage jitter, and FPGA edge-detection jitter. The total conversion dead time is below 300 ns for a 10 ns input range, about five times lower than a single-stage design with the same total stretching factor. The resolution bottleneck is the first-stage time-stretching jitter, not the counter quantization.

Load-bearing premise

The load-bearing premise is that the calibration look-up tables and constant edge-detection corrections, measured once on the bench, remain valid during the reported measurements and in real use, with no stability data for temperature, supply voltage, or aging.

Editorial extensions

If this is right

A 100 MHz clock is enough for sub-100 ps timing; the stretching stages, not clock speed, set the resolution.
Two-stage stretching cuts dead time by roughly the first-stage factor compared with a single-stage design, making hit rates of about 100 kHz feasible.
The first-stage time-stretching jitter, not counter quantization, is the current resolution limit, so reducing that jitter in an integrated design should improve resolution toward the sub-50 ps target.
Calibration look-up tables with about 2 ns step spacing give resolution comparable to dense calibration, so a simple on-chip calibration counter may suffice for a multi-channel ASIC.
The prototype already meets the timing needs of neutrino-detector photoelectron readout, where 100 ps precision suffices.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The one-time bench calibration with an oscilloscope is an unstated environmental assumption; temperature, supply-voltage, or aging drift would shift the stretching curves and degrade the reported 60–100 ps figures unless recalibration is added.
The reported 63 ps is measured against a 3 GHz oscilloscope reference, so part of the quoted jitter belongs to the reference; the TDC's intrinsic resolution may be somewhat better than the stated numbers.
The power argument is not demonstrated by this discrete prototype, which uses currents in the 10–100 mA range; the μW-per-channel claim depends on a CMOS implementation that inherits the same calibration and jitter properties.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Dear Colleague,

The two-stage time-stretching TDC architecture is genuinely neat: stretch the input by S0, count clock cycles, then stretch the two residual edge tails by S1 and S2, giving a total factor ~S0*S1 with dead time ~(S0+S1)*T instead of S0*S1*T. For a total factor of 100, that brings dead time from ~1 µs down to ~300 ns. The LSB formula T/S^2 is right, and the resolution budget in Eq. (4.2) adds up. The basic idea is sound and the prototype demonstrates it.

The measured 60–100 ps resolution is plausible. The scope waveforms show the expected charge/discharge behavior, the jitter histograms are clean, and the final 63 ps at 10 ns matches the component-level estimates. Using interpolation LUTs to handle the nonlinear current-source behavior is pragmatic and clearly described.

The soft spots are mostly around referencing and independence. The paper never cites the existing time-stretching TDC literature, so the novelty claim is under-argued. More importantly, the calibration LUTs and the final verification both use the same 3 GHz oscilloscope as the time reference. That makes the reported resolution a single-instrument result, and it also means Eq. (4.2) and Figure 13 are not independent checks of each other. A measurement against an independent time reference, or at least a characterization of the scope's own jitter contribution, would make the numbers much stronger. The constant edge-detection correction factor is introduced without a stability study; temperature and supply voltage are not scanned. The statistics are also thin—many histograms have only a few hundred events.

None of these are fatal for a proof-of-concept, and the paper says as much. The toy Monte Carlo for the calibration TDC quantization is a nice extra. For the HEP instrumentation community, this is a useful, honest data point for a low-power TDC path toward 4D pixels and neutrino readout.

Send it to peer review. It deserves a serious referee. I'd bring it to the next reading group and would cite it if I were writing about TDC architectures.

Referee Report

5 major / 5 minor

Summary. The manuscript describes a proof-of-concept two-stage time-stretching TDC built from discrete components. An input pulse is first stretched by a factor S0, digitized with a 100 MHz counter, and the two sub-clock-cycle residual edges are stretched again by S1 and S2 and digitized, yielding an effective LSB of about T/S^2 ≈ 100 ps. The prototype is characterized with a 3 GHz oscilloscope, including per-stage stretching linearity, jitter, and FPGA edge-detection jitter. The authors report a measured time resolution of 63 ps at 10 ns input width and 60–100 ps across 10–20 ns, with a predicted combined jitter of 67 ps from Eq. (4.2). The paper also presents a toy Monte Carlo study of calibration TDC requirements for a future ASIC implementation.

Significance. If the reported resolution and dead time are robust, the two-stage time-stretching architecture is a credible route toward low-power TDCs for pixel detectors, because it reduces the effective LSB with a slow counter and avoids the dead-time penalty of a single large stretching factor. The paper's strengths are the explicit decomposition of the error budget in Eq. (4.1), the calibration LUT approach with a demonstration that a coarse 2 ns calibration step is sufficient, and the toy MC study of calibration TDC precision. The work is transparent about the prototype's limitations, including nonlinearity and the fact that power consumption is not optimized. The main weakness is that the resolution claim is currently benchmarked against the same oscilloscope used for calibration, with no stability or independent-reference data.

major comments (5)

[§5 and Fig. 13] The headline resolution of 63 ps at 10 ns input width is measured by comparing the TDC reconstruction against 'true' widths obtained with the same 3 GHz oscilloscope that was used to generate the calibration look-up tables for S0, S1, and S2. This makes the result circular in the sense that no independent time reference is used, and any drift of the stretching nonlinearity or of the edge-detection correction between calibration and evaluation would be invisible. Please provide an out-of-sample validation, for example a calibrated time interval from a different source or a cross-measurement with a second TDC channel, and a repeatability/stability test with repeated calibrations over time and temperature, to support the claim that the 60–100 ps resolution is a property of the design rather than of one bench session.
[§4, edge-detection compensation paragraph] The text states that the fixed delay between edge-detection outputs and actual signal edges, and the constant offset between detected and true clock-edge distances, are 'compensated through a constant correction factor applied to the edge-detection outputs.' No numerical value, its uncertainty, or evidence of constancy across the operational range is provided. Since this correction enters directly into the reconstructed width in Eq. (2.4) and contributes to the resolution budget in Eq. (4.1), the omission leaves an unquantified systematic. Please report the measured correction factor with its statistical uncertainty and show that it is stable across the 10–20 ns input range and over the measurement campaign.
[§4, Eq. (4.2)] The combined resolution estimate of 67 ps in Eq. (4.2) uses jitter values (Figures 7, 11, 12) that are themselves measured with the same oscilloscope that provides the 'true' widths in Figure 13. Consequently, the agreement between 67 ps and the measured 63 ps is a consistency check, not an independent validation of the error budget. I ask the authors to state this explicitly or to derive at least one jitter contribution from an independent model, for example comparator noise or current-source noise, rather than from the same measurement chain.
[§4, Fig. 13 and related histograms] The statistical basis for the reported σ values is thin: the histograms in Figures 7, 10, and 13 appear to contain at most a few hundred entries, and no uncertainties on the fitted σ are quoted. Given that the central claim is sub-100 ps resolution, the σ values should be reported with statistical errors from the fit or from a bootstrap, and the number of events should be stated. This is necessary to distinguish the 60–100 ps range from a statistical fluctuation around, say, 80 ps.
[§4 and §6, dead-time claim] The abstract and Section 6 state that the conversion time for a 10 ns input width is below 300 ns, but this appears to be a derived quantity based on nominal stretching factors rather than a measured result. Since dead time is a key requirement for the intended high-rate applications, a direct double-pulse measurement showing the minimum interval between two accepted conversions would strengthen the paper. If such a measurement exists, it should be reported explicitly.

minor comments (5)

[Abstract and §4] The claim of 'under 100 ps' resolution should be qualified to the operational range of 10–20 ns, since Figure 13 (right) shows σ exceeding 100 ps for input widths above about 20 ns.
[§2, p. 3] There is a typo: 'An fast driver' should be 'A fast driver', and 'made withLT3092' is missing a space.
[Fig. 14 legend] The legend in Figure 14 repeats the same label twice ('σ by look up table from ~0.5 ns step size'); one copy should be removed or corrected.
[§2, after Eq. (2.3)] After giving the nominal stretching factor of 11, the text should explicitly note that the measured factors deviate from this value and that this is why interpolation-based look-up tables are needed.
[§4, Fig. 13 left] The mean of the distribution in Figure 13 (left) is −0.0261 ns; a brief comment on the source of this small bias would help the reader interpret the data.

Circularity Check

1 steps flagged · score 2.0 of 10

Calibration and final resolution share the same oscilloscope reference; Eq. (4.2) and Fig. 13 are an internal consistency check, not an independent prediction.

fitted input called prediction [Section 4, Eq. (4.2) and Fig. 13; Section 5, calibration description]
"The prototype TDC’s overall time resolution was measured by comparing direct oscilloscope measurements of input pulse widths with values reconstructed using equation (2.4). ... In the current implementation, we determine each unit’s stretching factor by injecting input signals and measuring both input and output pulse widths using a high-speed oscilloscope."

Equation (2.4) reconstructs the input width using look-up tables that were generated by measuring both input and output widths with the same high-speed oscilloscope, and Fig. 13 uses that same oscilloscope as the 'true' width reference. The reported resolution is therefore a residual relative to the very reference used to build the reconstruction; without a documented train/test split, it is an in-sample calibration residual rather than an out-of-sample validation. Equation (4.2) is also assembled from jitter values obtained with the same scope-based LUT method, so the agreement between Eq. (4.2) and Fig. 13 is an internal consistency check rather than a parameter-free prediction.

full rationale

No self-citations or imported uniqueness theorems are load-bearing, and the architectural derivation (Eqs. 2.3–2.5, dead-time analysis, quadrature model Eq. 4.1) is self-contained. The one mild circularity is that the LUTs embedded in Eq. (2.4) are calibrated with the same oscilloscope that later defines the 'true' widths in Fig. 13, and the jitter inputs to Eq. (4.2) come from the same scope-based method. This makes the reported resolution scope-relative and makes the 63 ps vs 67 ps agreement a consistency check, not an independent prediction. The measured jitter is still a physical quantity, and the LSB estimate follows from the clock period and measured stretching factors, so the claim does not reduce entirely to a fit. The uncharacterized stability of the calibration LUTs and the constant edge-correction factor is a real metrological limitation, but it is not itself a circularity.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The central claim depends on calibrated stretching behavior and on the assumption that the bench reference is much better than the TDC. No free parameter is adjusted to force the 63 ps result; the design constants I1, I2, C1 and vth are chosen for a nominal stretching factor of 10, and the actual per-unit curves are calibrated.

free parameters (6)

Capacitor C1 = about 0.48 nF (implied by I/C rates)
Chosen by hand for the 0.21 V/ns discharge rate; the stretching ratio and time scale depend on it.
Discharge current I2 = 100 mA
Selected to set the discharge rate; contributes to total power, which is not optimized in the discrete prototype.
Charge current I1 = 10 mA
Selected with I2 to give a nominal stretching factor of about 10.
Comparator threshold vth = 4.8 V
Sets the output pulse width and effective stretching factor; value chosen for the circuit in figure 1.
Calibration look-up tables for S0, S1, S2 = data-derived curves from figures 6 and 9
Each stretching unit's input-output relation is measured and interpolated; the final width reconstruction and resolution depend on these fitted curves.
Edge-detection correction factor = constant offset per edge
Section 4 applies a fixed correction to compensate delays between edge-detection outputs and true clock-edge distances; the value is inferred from scope measurements.

assumptions (5)

standard math Interpolation between calibration points approximates the true stretching curve.
The look-up table method in Section 5 assumes local linearity between measured calibration points.
domain assumption Jitter contributions are independent and can be added in quadrature.
Equation (4.1) combines LSB, stretching jitter, and edge-detection jitter as independent Gaussian sources, without evidence of correlations.
domain assumption The oscilloscope reference has negligible uncertainty compared with about 60 ps.
All calibration and resolution measurements use a 3 GHz, 20 GS/s RIGOL DS70304 as the reference, but its own jitter and timebase accuracy are not quantified.
domain assumption Calibration look-up tables and correction factors remain stable during the measurement session and in deployment.
Sections 4 and 5 rely on constant correction factors and calibration curves; no temperature, voltage, or aging studies are reported.
domain assumption The stretched-pulse counting and edge-detection logic runs correctly on the Intel MAX 10 FPGA at 100 MHz.
The prototype uses an FPGA eval kit as counter and edge detector; no FPGA timing closure or logic verification details are given.

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Cite this review

Pith. "Pith review of A two-stage time-stretching TDC with discrete components." pith.science (2026). https://pith.science/paper/BCVQQMFG

@misc{pith2026250507514,
  author       = {Pith},
  title        = {Pith review of: A two-stage time-stretching TDC with discrete components},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BCVQQMFG}},
  note         = {Machine review of arXiv:2505.07514}
}

abstract

This paper presents the design and testing of a time-stretching-based time-to-digital converter (TDC) implemented with discrete components. The TDC utilizes capacitor charging and discharging to achieve a time resolution of under 100 ps using a 100 MHz clock counter on a low-power, low-cost FPGA, achieving a time amplification factor of over 100. A two-stage time-stretching architecture is employed to reduce the conversion time to below 300 ns for a 10 ns input range. An onboard calibration system, including a pulse generation circuit, is implemented, and calibration results are presented. This system serves as a proof-of-concept platform for circuit optimization toward an ASIC implementation of a front-end TDC targeting future 4D pixel detectors at hadron colliders, with goals of sub-50 ps resolution and power consumption at the $\mu$W/channel level. Additionally, the design offers a modular, low-cost solution for extracting signal arrival times with 100 ps precision in particle physics experiments, such as photoelectron timing extraction for photodetector readout in neutrino experiments.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

9 extracted references · 2 canonical work pages

[1]

write newline

" write newline "" before.all 'output.state := FUNCTION blank.sep after.quote 'output.state := FUNCTION fin.entry output.state after.quoted.block = 'skip 'add.period if write newline FUNCTION new.block output.state before.all = 'skip output.state after.quote = after.quoted.block 'output.state := after.block 'output.state := if if FUNCTION new.sentence out...
[2]

CMS collaboration, A MIP Timing Detector for the CMS Phase-2 Upgrade , Tech. Rep. CERN-LHCC-2019-003, CMS-TDR-020 https://cds.cern.ch/record/2667167, CERN, Geneva (2019)

arXiv 2019
[3]

ATLAS collaboration, Technical Design Report: A High-Granularity Timing Detector for the ATLAS Phase-II Upgrade , Tech. Rep. CERN-LHCC-2020-007, ATLAS-TDR-031 https://cds.cern.ch/record/2719855, CERN, Geneva (2020)

arXiv 2020
[4]

W. Luo, Q. Liu, Y. Zheng, Z. Wang and S. Chen, Reconstruction algorithm for a novel Cherenkov scintillation detector , https://doi.org/10.1088/1748-0221/18/02/P02004 Journal of Instrumentation 18 (2023) P02004 [ https://arxiv.org/abs/arXiv:2209.13772 arXiv:2209.13772 ]

arXiv 2023
[5]

H. Yang, T. Xue, C. Xu, Q. Pan, B. Liang, G. Gong et al., A newly developed multi-kilo-channel high-speed and high-precision waveform digitization system for Jinping Neutrino Experiment , https://doi.org/https://doi.org/10.1016/j.nima.2025.170211 Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Asso...

work page arXiv 2025
[6]

Agapopoulou, L

C. Agapopoulou, L. Beresford, D. Boumediene, L. Castillo García, S. Conforti, C. de la Taille et al., Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector , https://doi.org/10.1088/1748-0221/18/08/P08019 Journal of Instrumentation 18 (2023) P08019 [ https://arxiv.org/abs/arXiv:2306.08949 arXiv:2306.08949 ]

arXiv 2023
[7]

ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade

X. Huang, Q. Sun, D. Gong, P. Gwak, D. Kim, J. Lee et al., ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade , https://doi.org/10.1088/1748-0221/19/09/P09019 Journal of Instrumentation 19 (2024) P09019 [ https://arxiv.org/abs/arXiv:2404.14207 arXiv:2404.14207 ]

work page Pith review arXiv 2024
[8]

Zhang, H

W. Zhang, H. Sun, C. Edwards, D. Gong, X. Huang, C. Liu et al., A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade , https://doi.org/10.1109/TNS.2021.3085564 IEEE Transactions on Nuclear Science 68 (2021) 1984 [ https://arxiv.org/abs/arXiv:2011.01222 arXiv:2011.01222 ]

arXiv 2021

Show all 9 references

[9]

ATLAS collaboration, Technical Design Report for the ATLAS Inner Tracker Pixel Detector , Tech. Rep. CERN-LHCC-2017-021, ATLAS-TDR-030 https://cds.cern.ch/record/2285585, CERN, Geneva (2017)

2017

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.

[1] [1]

write newline

" write newline "" before.all 'output.state := FUNCTION blank.sep after.quote 'output.state := FUNCTION fin.entry output.state after.quoted.block = 'skip 'add.period if write newline FUNCTION new.block output.state before.all = 'skip output.state after.quote = after.quoted.block 'output.state := after.block 'output.state := if if FUNCTION new.sentence out...

[2] [2]

CMS collaboration, A MIP Timing Detector for the CMS Phase-2 Upgrade , Tech. Rep. CERN-LHCC-2019-003, CMS-TDR-020 https://cds.cern.ch/record/2667167, CERN, Geneva (2019)

arXiv 2019

[3] [3]

ATLAS collaboration, Technical Design Report: A High-Granularity Timing Detector for the ATLAS Phase-II Upgrade , Tech. Rep. CERN-LHCC-2020-007, ATLAS-TDR-031 https://cds.cern.ch/record/2719855, CERN, Geneva (2020)

arXiv 2020

[4] [4]

W. Luo, Q. Liu, Y. Zheng, Z. Wang and S. Chen, Reconstruction algorithm for a novel Cherenkov scintillation detector , https://doi.org/10.1088/1748-0221/18/02/P02004 Journal of Instrumentation 18 (2023) P02004 [ https://arxiv.org/abs/arXiv:2209.13772 arXiv:2209.13772 ]

arXiv 2023

[5] [5]

H. Yang, T. Xue, C. Xu, Q. Pan, B. Liang, G. Gong et al., A newly developed multi-kilo-channel high-speed and high-precision waveform digitization system for Jinping Neutrino Experiment , https://doi.org/https://doi.org/10.1016/j.nima.2025.170211 Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Asso...

work page arXiv 2025

[6] [6]

Agapopoulou, L

C. Agapopoulou, L. Beresford, D. Boumediene, L. Castillo García, S. Conforti, C. de la Taille et al., Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector , https://doi.org/10.1088/1748-0221/18/08/P08019 Journal of Instrumentation 18 (2023) P08019 [ https://arxiv.org/abs/arXiv:2306.08949 arXiv:2306.08949 ]

arXiv 2023

[7] [7]

ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade

X. Huang, Q. Sun, D. Gong, P. Gwak, D. Kim, J. Lee et al., ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade , https://doi.org/10.1088/1748-0221/19/09/P09019 Journal of Instrumentation 19 (2024) P09019 [ https://arxiv.org/abs/arXiv:2404.14207 arXiv:2404.14207 ]

work page Pith review arXiv 2024

[8] [8]

Zhang, H

W. Zhang, H. Sun, C. Edwards, D. Gong, X. Huang, C. Liu et al., A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade , https://doi.org/10.1109/TNS.2021.3085564 IEEE Transactions on Nuclear Science 68 (2021) 1984 [ https://arxiv.org/abs/arXiv:2011.01222 arXiv:2011.01222 ]

arXiv 2021