A memristor-CMOS reconfigurable multiplier is introduced to enable flexible bit-width operations with reduced area via SPICE simulations on 180-nm CMOS.
Title resolution pending
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2019 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Reconfigurable multiplier architecture based on memristor-cmos with higher flexibility
A memristor-CMOS reconfigurable multiplier is introduced to enable flexible bit-width operations with reduced area via SPICE simulations on 180-nm CMOS.