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arxiv: 1907.09078 · v1 · pith:DRXLLH5Unew · submitted 2019-07-22 · 💻 cs.AR

Reconfigurable multiplier architecture based on memristor-cmos with higher flexibility

Seungbum Baek This is my paper

Pith reviewed 2026-05-24 18:09 UTC · model grok-4.3

classification 💻 cs.AR
keywords reconfigurable multipliermemristor-CMOSbit-width flexibilityhybrid circuitsdigital signal processingSPICE modelCMOS process
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The pith

A memristor-CMOS hybrid multiplier reconfigures itself for multiplication at different bit widths.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a reconfigurable multiplier using memristor and CMOS components that supports flexible multiplication tuned to various bit widths. This matters because digital signal processing systems often run multiple algorithms that need different levels of precision, making separate fixed multipliers inefficient in area. The hybrid circuit reduces overall hardware size while maintaining the ability to switch configurations. Performance is checked through simulations that apply the design to sample tasks and compare results against standard multipliers.

Core claim

The memristor-CMOS based reconfigurable multiplier provides flexible multiplication according to various bit-widths. Performance of the proposed multiplier is estimated with some applications and comparison with conventional multipliers, using memristor SPICE model and proprietary 180-nm CMOS process.

What carries the argument

Memristor-CMOS hybrid circuit arranged as a reconfigurable multiplier for variable bit-width operations.

If this is right

  • A single circuit replaces multiple fixed-width multipliers, lowering total area in DSP hardware.
  • Systems can run varied algorithms without swapping or adding separate multiplier units.
  • Simulation tools allow direct performance comparisons to conventional multiplier designs.
  • The hybrid approach supports estimation of metrics such as area and speed for practical use cases.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The design could support runtime precision changes in embedded signal processing without extra logic.
  • Extending the same hybrid structure to other arithmetic blocks might create larger adaptable processors.
  • Measured silicon results would test whether the simulated area savings hold after fabrication variations.
  • This points to hybrid memory-logic circuits as a route for hardware that adapts its precision on demand.

Load-bearing premise

The memristor SPICE model combined with the 180-nm CMOS process provides a sufficiently accurate representation of the proposed reconfigurable multiplier's behavior, area, and performance in fabricated hardware.

What would settle it

Fabricate the multiplier in 180-nm CMOS with memristors and measure its actual area, power, speed, and bit-width reconfiguration capability against the simulation predictions.

Figures

Figures reproduced from arXiv: 1907.09078 by Seungbum Baek.

Figure 1
Figure 1. Figure 1: Block diagram of a 1-bit structure of proposed multiplier. An exclusive-OR gate is used to enable or disable input data, A and B, to be propagated to full adder with control signals, CTRLV and CTRLH. It has been shown that memristors operating compositely can be used to generate nonlinear dynamics via coupling [19- 20], and as logical computational blocks. Memristor-CMOS logic is principally targeted into … view at source ↗
Figure 2
Figure 2. Figure 2: Block diagram of a memristor-CMOS based NAND and NOR gates : (a) NAND gate, (b) NOR gate. The approach can be extended to an array architecture having variable bit-width. 8-bit reconfigurable multiplier which consists of 64-block is shown in [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 5
Figure 5. Figure 5: Block diagram of data propagation process of a 4-bit multiplication on a proposed 8-bit multiplier. Blocks shown in gray are turned on by control signals and receive 4-bit input data. And blocks shown in black are turned off by control signals and used for data propagation tunnel. Multipliable area on proposed multiplier is decided by control signals. The area which is split into 2-bit parallel and split i… view at source ↗
Figure 3
Figure 3. Figure 3: Block diagram of a proposed 8-bit multiplier. The multiplier takes the form of ripple carry adder. Each of the blocks consist of a exclusive-OR gate, 3-input AND gate and a full adder introduced in [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: illustrates parallel multiplication of 5-bit and 3-bit on an 8-bit multiplier. Enabled and disabled blocks are decided by control signals. Blocks shown in gray are activated and for 5- bit multiplication. Blocks shown in black are also activated and for 3-bit multiplication. In these multiplications, the horizontal control signals are ‘11100000’ and the vertical control signals are ‘00011111’. If each of t… view at source ↗
Figure 8
Figure 8. Figure 8: Block diagram of a 4-point parallel input Fast Fourier Transform (FFT) circuit : (a) Overall FFT structure, (b) – (c) Block Radix and MULT. Twiddle factor, W, is random number in 8-bit on the simulation. TABLE II. PERFORMANCE EVALUATION OF PROPOSED MULTIPLIER THROUGH FIR FILTER AND FFT Memristor-CMOS proposed FIR filter FFT Bit-width [bit] 8 4+4 8 4+4 Delay [ns] 28.8 (1.00) 20.3 (0.70) 24.5 (1.00) 16.17 (0… view at source ↗
read the original abstract

Multiplication is an indispensable operation in most of digital signal processing systems. Recently, many systems need to execute different types of algorithms on a multiplier. Therefore, it needs complicated computation and large area occupation. In this regard a fixed multiplier is inefficient and the development of a reconfigurable multiplier becomes increasingly important. The advent of memristor-CMOS hybrid circuits provides an opportunity for reducing area occupation. This paper introduces memristor-CMOS based reconfigurable multiplier which provides flexible multiplication according to various bit-width. Performance of the proposed multiplier is estimated with some applications and comparison with conventional multipliers, using memristor SPICE model and proprietary 180-nm CMOS process.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes a memristor-CMOS hybrid reconfigurable multiplier that supports flexible multiplication across various bit-widths to reduce area in DSP systems. It evaluates the design via SPICE simulation of a memristor model paired with a proprietary 180-nm CMOS process and compares area/performance against conventional multipliers in selected applications.

Significance. A working reconfigurable multiplier in this technology could reduce area for variable-bit-width workloads, but the manuscript supplies no equations, circuit schematics, or quantitative simulation results, so the claimed advantages cannot be assessed.

major comments (2)
  1. [Abstract] Abstract: all performance, area, and flexibility claims rest on SPICE simulation of an unspecified memristor model with a proprietary 180-nm CMOS process; no calibration data, process-variation analysis, endurance modeling, or measured silicon results are referenced, so the reported advantages over conventional multipliers cannot be evaluated.
  2. [Full text (no equations or data tables present)] The manuscript contains no equations, timing diagrams, or table of area/power/delay numbers, preventing any check of the reconfigurability mechanism or the cross-application comparisons.
minor comments (1)
  1. Clarify the supported bit-width range and the exact reconfiguration mechanism (e.g., how memristor states control partial-product routing).

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive comments. We address each major point below and will revise the manuscript to provide the requested details on the simulation methodology, design equations, and quantitative results.

read point-by-point responses

  1. Referee: [Abstract] Abstract: all performance, area, and flexibility claims rest on SPICE simulation of an unspecified memristor model with a proprietary 180-nm CMOS process; no calibration data, process-variation analysis, endurance modeling, or measured silicon results are referenced, so the reported advantages over conventional multipliers cannot be evaluated.

    Authors: The abstract summarizes results from SPICE simulations using a standard memristor model and the proprietary 180-nm CMOS process. We agree that additional details are needed for evaluation. In the revision we will specify the exact memristor model parameters, include any available calibration information, discuss process variation effects based on the simulation setup, and provide the quantitative area, power, and delay numbers supporting the flexibility and area-reduction claims. Endurance modeling was not part of the original scope but can be noted as a limitation. Measured silicon results are unavailable because this is a simulation-based proposal. revision: yes

  2. Referee: [Full text (no equations or data tables present)] The manuscript contains no equations, timing diagrams, or table of area/power/delay numbers, preventing any check of the reconfigurability mechanism or the cross-application comparisons.

    Authors: We acknowledge that the submitted manuscript lacks equations, timing diagrams, circuit schematics, and tabulated simulation results. The revised version will include these elements: equations describing the bit-width reconfiguration logic, timing diagrams for the hybrid memristor-CMOS operation, and tables comparing area, power, and delay against conventional multipliers for the selected DSP applications. This will enable direct verification of the reconfigurability mechanism and the reported comparisons. revision: yes

standing simulated objections not resolved
  • Measured silicon results cannot be provided, as the evaluation relies exclusively on SPICE simulations rather than fabricated hardware.

Circularity Check

0 steps flagged

No circularity: architecture description and SPICE simulation contain no self-referential derivations or fitted predictions.

full rationale

The paper describes a memristor-CMOS reconfigurable multiplier architecture and reports area/performance estimates obtained from SPICE simulation using an external memristor model plus a proprietary 180-nm CMOS process. No equations, first-principles derivations, parameter fits, or predictions appear in the abstract or are referenced in the provided context. The central claims rest on the simulation results themselves rather than on any reduction of outputs to inputs by construction, self-citation chains, or ansatz smuggling. This is the normal case for a circuit-architecture paper whose claims are externally falsifiable via fabrication or independent modeling.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review provides no equations or design details from which to extract free parameters, axioms, or invented entities.

pith-pipeline@v0.9.0 · 5627 in / 1043 out tokens · 24335 ms · 2026-05-24T18:09:39.716207+00:00 · methodology

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Reference graph

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