A training-free method that combines zero-weight bit-cell repair with per-column sign flips to make ternary LLMs on compute-in-memory accelerators substantially more tolerant to stuck-at faults.
A heterogeneous and programmable compute-in-memory accelerator architecture for analog-ai using dense 2-d mesh,
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ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs
A training-free method that combines zero-weight bit-cell repair with per-column sign flips to make ternary LLMs on compute-in-memory accelerators substantially more tolerant to stuck-at faults.