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ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs

T0 review · 2 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read ReTern combines column-wise sign flips with a redundant bit-cell state to recover most perplexity lost to stuck-at faults in ternary LLMs, at under 3% energy overhead.

desk verdict A sound, modest extension of the authors' TFix work; the main caveat is that its headline fault-tolerance numbers apply only to feedforward weights under a hybrid architecture. read the letter →

arxiv 2506.01140 v1 pith:CXRXOPWZ submitted 2025-06-01 cs.AR

Akul Malhotra , Sumeet Kumar Gupta This is my paper · ORCID
classification cs.AR
keywords ternaryLLMscompute-in-memorystuck-atfaultsfaulttolerancesigntransformationBitNetb1.58TCiMweightsparsity
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

ReTern is a training-free method for making ternary large language models resilient to stuck-at faults in ternary compute-in-memory (TCiM) accelerators. When memory cells get permanently stuck at 0 or 1, the −1/0/+1 weights of BitNet b1.58 models are corrupted and perplexity degrades sharply. ReTern repairs the damage in two complementary ways: zero-fix reprograms a redundant bit-cell state so zero weights survive single faults, and fault-aware sign transformations (FAST) flip entire weight columns and negate the output so stuck cells mask instead of corrupt. On Wikitext this cuts fault-induced perplexity degradation by about 35% for the 700M model and 25% for the 3B model at a 10% fault rate, with under 3% energy, under 7% latency, and under 1% area overhead. This matters because ternary LLMs are a leading candidate for edge deployment, yet their low weight sparsity defeats earlier zero-only fault-correction schemes.

What carries the argument

The load-bearing identity is the differential bit-cell encoding $W = M_1 - M_2$, where two binary memory elements realize three weight states and leave one unused state, 11, that behaves like the 00 zero state because equal discharges on both bitlines cancel. That redundancy is what zero-fix re-programs. The second mechanism is FAST, a per-column sign flip: for each column the algorithm measures $|w_{hw} - w_{ideal}|$ against $|w_{hw,flipped} + w_{ideal}|$ and stores the standard or negated column, tracked by a col_flip bit; the output subtractor then routes $x-y$ or $y-x$. Together they cover faults in both zero and non-zero weights, which is what makes the method work at the low sparsity levels of ternary LLMs.

What would settle it

Inject the same 5% and 10% stuck-at fault rates into the query, key, and value projection weights (or into the digital attention datapath) and re-run the Wikitext perplexity comparison; ReTern's reported improvements would shrink or disappear because FAST and zero-fix are applied only to the feedforward columns stored in TCiM arrays.

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Extended reading notes

Core claim

The paper's central claim is that combining per-column sign flipping with the unused '11' bit-cell state restores most of the accuracy that stuck-at faults take away from ternary LLMs, without retraining. A TCiM bitcell stores a ternary weight as $W = M_1 - M_2$ with two binary memory elements; the 11 state is functionally equivalent to 00 for the zero weight, giving a free second encoding. Zero-fix uses that redundancy to repair single faults in zero weights, while FAST compares, for each column, the summed $|w_{hw} - w_{ideal}|$ errors under the standard and negated encodings and picks the smaller, recording the choice in a one-bit col_flip vector whose output negation keeps the matrix multiply correct. Because zero-fix and FAST touch disjoint weight values, they compose cleanly. The paper reports that this recovers roughly 35% (700M) and 25% (3B) of the Wikitext perplexity degradation at a 10% stuck-at-fault rate, with small accuracy gains on PIQA and ARC (easy).

Load-bearing premise

All stuck-at faults are assumed to hit only the feedforward-layer ternary weights stored in TCiM arrays, while self-attention runs on fault-free digital compute; if faults also corrupt attention weights or digital logic, the reported 35% and 25% perplexity improvements would not cover the full model.

Editorial extensions

If this is right

  • Deploying ReTern on a 64x64 TCiM macro costs less than 3% energy, 7% latency, and 1% area, with the same peripheral structure across SRAM, ReRAM, and FeFET arrays.
  • ReTern remains training-free and requires only the SAF diagnosis information plus the pre-trained weights; no fine-tuning or labeled data is needed.
  • The technique should transfer in principle to other ternary precision models, including CNNs and transformers, because FAST is sparsity-independent and zero-fix simply uses the bit-cell redundancy.
  • Because zero-fix and FAST act on disjoint weight sets (zeros versus ±1), the two steps can be applied in any order without interfering.
  • Larger ternary LLMs (3B) already show more intrinsic tolerance to SAFs than the 700M model, and ReTern still adds a meaningful improvement on top.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: because FAST operates at column granularity, its benefit should shrink as TCiM arrays get taller, since one sign flip must serve more weights; the paper acknowledges this trade-off but leaves it unquantified, so measuring perplexity recovery at 128 and 256 rows would directly probe the method's practical ceiling.
  • Editorial inference: because SAFs are assumed absent from attention weights and digital logic, the 35% and 25% figures likely represent an upper bound for a fully analog implementation; extending FAST to dynamically generated Q/K/V matrices would require a different mechanism, since those weights are not static.
  • Editorial inference: the col_flip vector is effectively one sign bit per column, so ReTern can be seen as recycling the unused bit-cell state plus a cheap per-column sign bit to buy fault tolerance, which suggests a natural comparison against column-level error-correcting codes with the same overhead.
  • Editorial inference: a testable extension is to apply ReTern to 4-bit-activation ternary LLMs, where the activation quantizer changes the error landscape and may alter which column-flip choices are optimal.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper proposes ReTern, a training-free post-mapping technique for mitigating stuck-at faults (SAFs) in ternary compute-in-memory (TCiM) accelerators used for ternary LLM inference. ReTern combines zero-fix, which re-encodes zero weights using an alternate redundant bitcell state, with fault-aware sign transformation (FAST), which flips the sign of an entire column of weights and compensates by negating the corresponding dot-product output. The authors evaluate the method on BitNet b1.58 700M and 3B models, using Wikitext perplexity and PIQA/ARC-easy accuracy, under randomly injected SAFs at 5% and 10% rates. They report a 35% relative improvement in Wikitext perplexity for the 700M model at 10% SAF, and macro-level hardware overheads of 2.0-2.2% energy, 3.2-6.6% latency, and <1% area across SRAM, ReRAM, and FeFET TCiM arrays.

Significance. The proposed technique is practically appealing because it is training-free, requires only two 2:1 multiplexers and a per-column flip register, and is evaluated on publicly available pretrained ternary LLMs across three tasks and two fault rates. The identification of TFix's limited effectiveness on low-sparsity ternary LLMs is a useful contribution, and the explicit combination of zero-fix and FAST is a simple but effective extension. If the results are reproducible, ReTern would be a strong candidate for SAF mitigation in edge TCiM LLM accelerators. However, the headline fault-tolerance numbers are obtained under a restricted fault model (feedforward-only SAFs), and the 'perplexity reduction' metric is not precisely defined, which limits the strength of the claims as stated.

major comments (2)
  1. [IV-A and Abstract/Conclusion] The fault model in Section IV-A injects SAFs only into feedforward-layer ternary weights, with self-attention layers assumed SAF-free and running on digital compute cores. This restriction is not stated in the abstract or the conclusion, where the results are summarized as applying to 'ternary LLMs' and 'TCiM accelerators' generally. Since BitNet b1.58 also contains ternarized attention projection weights, the reported 35%/25% figures cannot be interpreted as full-model SAF tolerance under a general TCiM mapping. Please add an explicit scope statement in the abstract and conclusion, or better, include an additional experiment or discussion that addresses SAFs in attention weights (e.g., a sensitivity study with attention arrays also faulted) to quantify the limitation.
  2. [IV-B] The text reports '35%' and '25%' reductions in Wikitext perplexity without specifying whether these are reductions in absolute perplexity from the faulty baseline or reductions in the SAF-induced perplexity degradation relative to the ideal model. These interpretations lead to different quantitative claims; for example, the 700M model at 10% SAF degrades from roughly 12 to roughly 26, so a 35% absolute reduction would give about 16.9, while a 35% reduction in degradation would give about 21.1. Please define the metric and report the underlying median or mean perplexity values (e.g., in a table) so that the claimed benefit can be verified unambiguously.
minor comments (5)
  1. [Algorithm 1 and Eq. (5)] The algorithm does not explicitly define whw_flipped before Eq. (5); please state that for the flipped option, the hardware-mapped weights are computed by applying the SAF map to -Wideal, and clarify the notation in the pseudocode.
  2. [Section III-A] The notation for zero-weight encodings is confusing: the text says the '11' state is referred to as '01'. Use explicit M1M2 bit-pattern notation throughout (e.g., 00 and 11) to avoid ambiguity about which memory element is programmed.
  3. [Section IV-B] The paper does not report confidence intervals or statistical significance for the 5% SAF-rate improvements, which appear to be small (6-10%); please indicate whether these differences are within the Monte Carlo variance shown in the box plots.
  4. [Section IV-C] The PTM reference [34] is given only as a URL with no document title; please provide a complete citation with title and access date.
  5. [Section II-D and Fig. 2] The sparsity comparison in Fig. 2 mixes previously reported sparsities from various ternary CNN/DNN models with the BitNet LLMs; since model architecture and sparsity definitions may differ, please state the source and definition of each sparsity value, and report feedforward-layer sparsity separately if that is where SAFs are injected.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: ReTern's FAST and zero-fix are evaluated against independent perplexity and accuracy metrics, and the only reuse of prior self-authored work (TFix) is as a component and baseline, not as justification.

full rationale

The central claim is measured, not derived from a fitted target: Algorithm 1 selects column flips by comparing errstandard = Σ|whw − wideal| with errflipped = Σ|whw_flipped + wideal| (Eqs. 4–5), and Section IV-B then reports Wikitext perplexity, PIQA, and ARC (easy) results after fault injection. No parameter is fitted to the perplexity metric itself, so the reported 35% and 25% reductions are not forced by construction. The zero-fix component is attributed to the authors' prior TFix [21], but the manuscript independently explains the mechanism ('the 11 state would produce a voltage drop of Δ on both BL1 and BL2 ... cancel out'), and TFix is explicitly used as a baseline in the experiments; this is component reuse rather than load-bearing self-citation. The main caveat, that SAFs are injected only into feedforward-layer ternary weights while self-attention runs fault-free on digital cores (Section IV-A), limits the generality of the fault-tolerance claim but is a scope and correctness concern rather than a circularity. Overall, the derivation chain is self-contained and the empirical evaluation is independent of the optimization objective.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No numeric quantity is fitted to target perplexity or accuracy; the method's only degree of freedom is a binary per-column flip decision chosen by the L1 error metrics in Eq. (4)-(5). The listed axioms are hardware and fault-model assumptions inherited from the TCiM design and evaluation framework.

assumptions (5)
  • domain assumption Two binary memory elements per ternary weight with W = M1 - M2, and the unused '11' state is functionally equivalent to zero.
    Adopted from the TCiM bitcell design in Section II-B, Fig. 1; zero-fix depends on '11' being writable and producing zero output.
  • domain assumption SAFs are randomly and uniformly distributed across array cells, and only unmasked faults (where stored value differs from stuck state) corrupt output.
    Fault injection model in Section IV-A; the paper also neglects the low probability of two SAFs in a single bitcell.
  • domain assumption Fault diagnosis is exact, providing correct position and type of every SAF before mapping.
    Algorithm 1 Step 1 assumes SAF information from diagnosis; no diagnosis-error rate is modeled in Section III-C.
  • domain assumption All SAFs occur only in feedforward-layer weights stored in TCiM; self-attention runs on fault-free digital cores.
    Explicit architecture assumption in Section IV-A; limits the scope of the reported perplexity reduction.
  • domain assumption Hardware peripheral and memory models (PTM, NeuroSim, compact ReRAM/FeFET models) accurately represent 7nm TCiM energy, latency, and area.
    Overhead numbers in Table I rely on simulations from references [34]-[42] rather than silicon measurements.

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Cite this review

Pith. "Pith review of ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs." pith.science (2026). https://pith.science/paper/CXRXOPWZ

@misc{pith2026250601140,
  author       = {Pith},
  title        = {Pith review of: ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CXRXOPWZ}},
  note         = {Machine review of arXiv:2506.01140}
}
read the original abstract

Ternary large language models (LLMs), which utilize ternary precision weights and 8-bit activations, have demonstrated competitive performance while significantly reducing the high computational and memory requirements of full-precision LLMs. The energy efficiency and performance of Ternary LLMs can be further improved by deploying them on ternary computing-in-memory (TCiM) accelerators, thereby alleviating the von-Neumann bottleneck. However, TCiM accelerators are prone to memory stuck-at faults (SAFs) leading to degradation in the model accuracy. This is particularly severe for LLMs due to their low weight sparsity. To boost the SAF tolerance of TCiM accelerators, we propose ReTern that is based on (i) fault-aware sign transformations (FAST) and (ii) TCiM bit-cell reprogramming exploiting their natural redundancy. The key idea is to utilize FAST to minimize computations errors due to SAFs in +1/-1 weights, while the natural bit-cell redundancy is exploited to target SAFs in 0 weights (zero-fix). Our experiments on BitNet b1.58 700M and 3B ternary LLMs show that our technique furnishes significant fault tolerance, notably 35% reduction in perplexity on the Wikitext dataset in the presence of faults. These benefits come at the cost of < 3%, < 7%, and < 1% energy, latency and area overheads respectively.

Figures

Figures reproduced from arXiv: 2506.01140 by the authors.

Figure 1
Figure 1. The high-precision activation I is bit-streamed on W L1 and is binary (0 or VDD) per cycle. In case I is signed, it can be bit-streamed in 2’s complement encoding. Since two binary elements can represent four possible states, each bitcell has a natural redundancy in the form of an unused state, which corresponds to M1 = M2 = 1. We refer to this redundancy as natural since it is a consequence of implementing a ternar… view at source ↗
Figure 1
Figure 1. TCiM bitcell with its input and weight encoding. The [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. Zero-fix, wherein, when an ideal zero weight ( [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (2 more)
Figure 5
Figure 5. Figure 5: (a) Modified TCiM array to make it compatible with [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Performance results for the 700M BitNet 1.58b model. [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.