Experimental realization of lattice surgery on two d=3 surface-code logical qubits in superconducting hardware, with logical Bell state, Deutsch-Jozsa algorithm, and conditioned non-Clifford gate fidelity of 0.943.
Demonstrating real-time and low-latency quantum error correction with superconducting qubits
12 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
abstract
Quantum error correction (QEC) will be essential to achieve the accuracy needed for quantum computers to realise their full potential. The field has seen promising progress with demonstrations of early QEC and real-time decoded experiments. As quantum computers advance towards demonstrating a universal fault-tolerant logical gate set, implementing scalable and low-latency real-time decoding will be crucial to prevent the backlog problem, avoiding an exponential slowdown and maintaining a fast logical clock rate. Here, we demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of a superconducting quantum processor. We perform an 8-qubit stability experiment with up to $25$ decoding rounds and a mean decoding time per round below $1$ ${\mu}s$, showing that we avoid the backlog problem even on superconducting hardware with the strictest speed requirements. We observe logical error suppression as the number of decoding rounds is increased. We also implement and time a fast-feedback experiment demonstrating a decoding response time of $9.6$ ${\mu}s$ for a total of $9$ measurement rounds. The decoder throughput and latency developed in this work, combined with continued device improvements, unlock the next generation of experiments that go beyond purely keeping logical qubits alive and into demonstrating building blocks of fault-tolerant computation, such as lattice surgery and magic state teleportation.
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Syndrome resampling increases QEC thresholds and cuts logical errors by up to four orders of magnitude by biasing toward likely syndromes, linked to Rényi coherent information phase transitions.
First end-to-end demonstration of quantum error correction integrated with quantum phase estimation to compute molecular hydrogen ground-state energy to 0.001(13) hartree accuracy on Quantinuum H2-2 hardware.
The paper defines covert quantum computing via quantum strategies, proves O(sqrt(n)) border qubits suffice for detection in planar n-qubit circuits with nearest-neighbor crosstalk, and experimentally detects additional long-range coupling on IQM Emerald and IBM Heron processors.
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
Triage is an adaptive parallel window decoding scheduler that reduces average logical error rates by 52.6% compared to standard temporal parallelism while keeping stalls low under scarce classical resources.
O3LS reduces space overhead by up to 46.7% and time overhead by up to 36% in lattice surgery while suppressing logical error rates by up to an order of magnitude compared with prior layout and scheduling approaches.
Distance-4 bivariate bicycle codes plus an interleaved feed-forward decoder give a 29-physical-qubit encoding of a 4-qubit QCNN that is more noise-resilient than the bare circuit at 0.1% error rates.
A 4 K hybrid photonic/CMOS controller distributes optical pulse templates while using local Cryo-CMOS for amplitude, phase, and timing control to reduce per-channel dissipation and enable scalable qubit gates.
Phase noise near the Rabi frequency, not high-frequency noise, dominates qubit fidelity loss, according to Qiskit-Dynamics simulations.
A white paper proposing a six-layer system stack for real-time quantum error correction, with benchmarks of decoders for surface and qLDPC codes and latency models.
The paper identifies four key hurdles in the transition from NISQ to FASQ quantum computers and argues that targeting them will accelerate progress toward useful quantum advantage.
citing papers explorer
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A superconducting surface-code processor with lattice-surgery logical operations
Experimental realization of lattice surgery on two d=3 surface-code logical qubits in superconducting hardware, with logical Bell state, Deutsch-Jozsa algorithm, and conditioned non-Clifford gate fidelity of 0.943.
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Syndrome resampling enhances quantum error correction thresholds
Syndrome resampling increases QEC thresholds and cuts logical errors by up to four orders of magnitude by biasing toward likely syndromes, linked to Rényi coherent information phase transitions.
-
Quantum Error-Corrected Computation of Molecular Energies
First end-to-end demonstration of quantum error correction integrated with quantum phase estimation to compute molecular hydrogen ground-state energy to 0.001(13) hartree accuracy on Quantinuum H2-2 hardware.
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Toward Covert Quantum Computing
The paper defines covert quantum computing via quantum strategies, proves O(sqrt(n)) border qubits suffice for detection in planar n-qubit circuits with nearest-neighbor crosstalk, and experimentally detects additional long-range coupling on IQM Emerald and IBM Heron processors.
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Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
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Triage: An Adaptive Parallel Window Decoding Scheduler for Real-time Fault-Tolerant Quantum Computation
Triage is an adaptive parallel window decoding scheduler that reduces average logical error rates by 52.6% compared to standard temporal parallelism while keeping stalls low under scarce classical resources.
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O3LS: Optimizing Lattice Surgery via Automatic Layout Searching and Loose Scheduling
O3LS reduces space overhead by up to 46.7% and time overhead by up to 36% in lattice surgery while suppressing logical error rates by up to an order of magnitude compared with prior layout and scheduling approaches.
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Low-Overhead Error-Corrected QCNNs Using Bivariate Bicycle Codes
Distance-4 bivariate bicycle codes plus an interleaved feed-forward decoder give a 29-physical-qubit encoding of a 4-qubit QCNN that is more noise-resilient than the bare circuit at 0.1% error rates.
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A Cryogenic Hybrid Photonic/CMOS Controller Architecture for Scalable Superconducting Qubit Control
A 4 K hybrid photonic/CMOS controller distributes optical pulse templates while using local Cryo-CMOS for amplitude, phase, and timing control to reduce per-channel dissipation and enable scalable qubit gates.
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Impact of control signal phase noise on qubit fidelity
Phase noise near the Rabi frequency, not high-frequency noise, dominates qubit fidelity loss, according to Qiskit-Dynamics simulations.
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Real-Time Quantum Error Correction System Stack: Architecture, Algorithms, and Engineering Practice
A white paper proposing a six-layer system stack for real-time quantum error correction, with benchmarks of decoders for surface and qLDPC codes and latency models.
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Mind the gaps: The fraught road to quantum advantage
The paper identifies four key hurdles in the transition from NISQ to FASQ quantum computers and argues that targeting them will accelerate progress toward useful quantum advantage.