Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
A deep learning framework for verilog autocompletion towards design and verification automation
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VerilogCL applies contrastive learning with minimal-error data pairs and a proactive screening module to improve compilation success and functional correctness of 7B LLM-generated Verilog over open-source and commercial baselines on VerilogEval and RTLLM benchmarks.
citing papers explorer
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Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
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VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
VerilogCL applies contrastive learning with minimal-error data pairs and a proactive screening module to improve compilation success and functional correctness of 7B LLM-generated Verilog over open-source and commercial baselines on VerilogEval and RTLLM benchmarks.